參數(shù)資料
型號： XC5VFX100T-2FFG1136C
廠商： Xilinx Inc
文件頁數(shù)： 13/13頁
文件大小： 0K
描述： IC FPGA VIRTEX 5 100K 1136FFGBGA
標準包裝： 1
系列： Virtex®-5 FXT
LAB/CLB數(shù)： 8000
邏輯元件/單元數(shù)： 102400
RAM 位總計： 8404992
輸入/輸出數(shù)： 640
電源電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 1136-BBGA，F(xiàn)CBGA
供應商設備封裝： 1136-FCBGA
配用： 568-5088-ND - BOARD DEMO DAC1408D750
Virtex-5 Family Overview
DS100 (v5.0) February 6, 2009
Product Specification
9
R
Virtex-5 LXT, SXT, TXT, and FXT Platform Features
This section briefly describes blocks available only in LXT, SXT, TXT, and FXT devices.
Tri-Mode (10/100/1000 Mb/s) Ethernet MACs
Virtex-5 LXT, SXT, TXT, and FXT devices contain up to eight
embedded Ethernet MACs, two per Ethernet MAC block.
The blocks have the following characteristics:
Designed to the IEEE 802.3-2002 specification
UNH-compliance tested
RGMII/GMII Interface with SelectIO or SGMII interface
when used with RocketIO transceivers
Half or full duplex
Supports Jumbo frames
1000 Base-X PCS/PMA: When used with RocketIO
GTP transceiver, can provide complete 1000 Base-X
implementation on-chip
DCR-bus connection to microprocessors
Integrated Endpoint Blocks for PCI Express
Virtex-5 LXT, SXT, TXT, and FXT devices contain up to four
integrated Endpoint blocks. These blocks implement
Transaction Layer, Data Link Layer, and Physical Layer
functions to provide complete PCI Express Endpoint
functionality with minimal FPGA logic utilization. The blocks
have the following characteristics:
Compliant with the PCI Express Base Specification 1.1
Works in conjunction with RocketIO transceivers to
provide complete endpoint functionality
1, 4, or 8 lane support per block
Virtex-5 LXT and SXT Platform Features
This section briefly describes blocks available only in LXT and SXT devices.
RocketIO GTP Transceivers
4 - 24 channel RocketIO GTP transceivers capable of
running 100 Mb/s to 3.75 Gb/s.
Full clock and data recovery
8/16-bit or 10/20-bit datapath support
Optional 8B/10B or FPGA-based encode/decode
Integrated FIFO/elastic buffer
Channel bonding and clock correction support
Embedded 32-bit CRC generation/checking
Integrated comma-detect or A1/A2 detection
Programmable pre-emphasis (AKA transmitter
equalization)
Programmable transmitter output swing
Programmable receiver equalization
Programmable receiver termination
Embedded support for:
Out of Band (OOB) signalling: Serial ATA
Beaconing, electrical idle, and PCI Express receiver
detection
Built-in PRBS generator/checker
Virtex-5 FPGA RocketIO GTP transceivers are further
discussed in the Virtex-5 FPGA RocketIO GTP Transceiver
User Guide.
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相關代理商/技術參數(shù)
參數(shù)描述
XC5VFX100T-2FFG1136CES 制造商:Xilinx 功能描述:
XC5VFX100T-2FFG1136I 功能描述:IC FPGA VIRTEX 5 100K 1136FFGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-5 FXT 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55）
XC5VFX100T-2FFG1738C 功能描述:IC FPGA VIRTEX 5 100K 1738FFGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-5 FXT 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55）
XC5VFX100T-2FFG1738CES 制造商:Xilinx 功能描述:
XC5VFX100T-2FFG1738I 功能描述:IC FPGA VIRTEX 5 100K 1738FFGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-5 FXT 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55）
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