參數(shù)資料
型號: XC5VFX200T-1FFG1738C
廠商: Xilinx Inc
文件頁數(shù): 6/13頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX 5 200K 1738FFGBGA
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 FXT
LAB/CLB數(shù): 15360
邏輯元件/單元數(shù): 196608
RAM 位總計(jì): 16809984
輸入/輸出數(shù): 960
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1738-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1738-FCBGA
配用: 568-5088-ND - BOARD DEMO DAC1408D750
Virtex-5 Family Overview
2
DS100 (v5.0) February 6, 2009
Product Specification
R
Table 1: Virtex-5 FPGA Family Members
Device
Configurable Logic Blocks (CLBs)
DSP48E
Slices(2)
Block RAM Blocks
CMTs(4)
PowerPC
Processor
Blocks
Endpoint
Blocks for
PCI
Express
Ethernet
MACs(5)
Max RocketIO
Transceivers(6)
Total
I/O
Banks(8)
Max
User
I/O(7)
Array
(Row x Col)
Virtex-5
Slices(1)
Max
Distributed
RAM (Kb)
18 Kb(3) 36 Kb
Max
(Kb)
GTP
GTX
XC5VLX30
80 x 30
4,800
320
32
64
32
1,152
2
N/A
13
400
XC5VLX50
120 x 30
7,200
480
48
96
48
1,728
6
N/A
17
560
XC5VLX85
120 x 54
12,960
840
48
192
96
3,456
6
N/A
17
560
XC5VLX110
160 x 54
17,280
1,120
64
256
128
4,608
6
N/A
23
800
XC5VLX155
160 x 76
24,320
1,640
128
384
192
6,912
6
N/A
23
800
XC5VLX220
160 x 108
34,560
2,280
128
384
192
6,912
6
N/A
23
800
XC5VLX330
240 x 108
51,840
3,420
192
576
288
10,368
6
N/A
33
1,200
XC5VLX20T
60 x 26
3,120
210
24
52
26
936
1
N/A
1
2
4
N/A
7
172
XC5VLX30T
80 x 30
4,800
320
32
72
36
1,296
2
N/A
1
4
8
N/A
12
360
XC5VLX50T
120 x 30
7,200
480
48
120
60
2,160
6
N/A
1
4
12
N/A
15
480
XC5VLX85T
120 x 54
12,960
840
48
216
108
3,888
6
N/A
1
4
12
N/A
15
480
XC5VLX110T
160 x 54
17,280
1,120
64
296
148
5,328
6
N/A
1
4
16
N/A
20
680
XC5VLX155T
160 x 76
24,320
1,640
128
424
212
7,632
6
N/A
1
4
16
N/A
20
680
XC5VLX220T 160 x 108
34,560
2,280
128
424
212
7,632
6
N/A
1
4
16
N/A
20
680
XC5VLX330T 240 x 108
51,840
3,420
192
648
324
11,664
6
N/A
1
4
24
N/A
27
960
XC5VSX35T
80 x 34
5,440
520
192
168
84
3,024
2
N/A
1
4
8
N/A
12
360
XC5VSX50T
120 x 34
8,160
780
288
264
132
4,752
6
N/A
1
4
12
N/A
15
480
XC5VSX95T
160 x 46
14,720
1,520
640
488
244
8,784
6
N/A
1
4
16
N/A
19
640
XC5VSX240T
240 x 78
37,440
4,200
1,056
1,032
516
18,576
6
N/A
1
4
24
N/A
27
960
XC5VTX150T
200 x 58
23,200
1,500
80
456
228
8,208
6
N/A
1
4
N/A
40
20
680
XC5VTX240T
240 x 78
37,440
2,400
96
648
324
11,664
6
N/A
1
4
N/A
48
20
680
XC5VFX30T
80 x 38
5,120
380
64
136
68
2,448
2
1
4
N/A
8
12
360
XC5VFX70T
160 x 38
11,200
820
128
296
148
5,328
6
1
3
4
N/A
16
19
640
XC5VFX100T
160 x 56
16,000
1,240
256
456
228
8,208
6
2
3
4
N/A
16
20
680
XC5VFX130T
200 x 56
20,480
1,580
320
596
298
10,728
6
2
3
6
N/A
20
24
840
XC5VFX200T
240 x 68
30,720
2,280
384
912
456
16,416
6
2
4
8
N/A
24
27
960
Notes:
1.
Virtex-5 FPGA slices are organized differently from previous generations. Each Virtex-5 FPGA slice contains four LUTs and four flip-flops (previously
it was two LUTs and two flip-flops.)
2.
Each DSP48E slice contains a 25 x 18 multiplier, an adder, and an accumulator.
3.
Block RAMs are fundamentally 36 Kbits in size. Each block can also be used as two independent 18-Kbit blocks.
4.
Each Clock Management Tile (CMT) contains two DCMs and one PLL.
5.
This table lists separate Ethernet MACs per device.
6.
RocketIO GTP transceivers are designed to run from 100 Mb/s to 3.75 Gb/s. RocketIO GTX transceivers are designed to run from 150Mb/s to
6.5 Gb/s.
7.
This number does not include RocketIO transceivers.
8.
Includes configuration Bank 0.
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