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參數(shù)資料
| 型號(hào)： | XC5VFX70T-1FF1136I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 12/13頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA VIRTEX-5FXT 1136FFBGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | Virtex®-5 FXT |
| LAB/CLB數(shù)： | 5600 |
| 邏輯元件/單元數(shù)： | 71680 |
| RAM 位總計(jì)： | 5455872 |
| 輸入/輸出數(shù)： | 640 |
| 電源電壓： | 0.95 V ~ 1.05 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 1136-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 1136-FCBGA |
| 配用： | 568-5088-ND - BOARD DEMO DAC1408D750 |
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Virtex-5 Family Overview
8
DS100 (v5.0) February 6, 2009
Product Specification
R
Global Clocking
The CMTs and global-clock multiplexer buffers provide a
complete solution for designing high-speed clock networks.
Each CMT contains two DCMs and one PLL. The DCMs
and PLLs can be used independently or extensively
cascaded. Up to six CMT blocks are available, providing up
to eighteen total clock generator elements.
Each DCM provides familiar clock generation capability. To
generate deskewed internal or external clocks, each DCM
can be used to eliminate clock distribution delay. The DCM
also provides 90°, 180°, and 270° phase-shifted versions of
the output clocks. Fine-grained phase shifting offers higher-
resolution phase adjustment with fraction of the clock period
increments. Flexible frequency synthesis provides a clock
output frequency equal to a fractional or integer multiple of
the input clock frequency.
To augment the DCM capability, Virtex-5 FPGA CMTs also
contain a PLL. This block provides reference clock jitter
filtering and further frequency synthesis options.
Virtex-5 devices have 32 global-clock MUX buffers. The
clock tree is designed to be differential. Differential clocking
helps reduce jitter and duty cycle distortion.
DSP48E Slices
DSP48E slice resources contain a 25 x 18 two’s
complement multiplier and a 48-bit
adder/subtacter/accumulator. Each DSP48E slice also
contains extensive cascade capability to efficiently
implement high-speed DSP algorithms.
The Virtex-5 FPGA DSP48E slice features are further
discussed in Virtex-5 FPGA XtremeDSP Design
Considerations.
Routing Resources
All components in Virtex-5 devices use the same
interconnect scheme and the same access to the global
routing matrix. In addition, the CLB-to-CLB routing is
designed to offer a complete set of connectivity in as few
hops as possible. Timing models are shared, greatly
improving the predictability of the performance for high-
speed designs.
Boundary Scan
Boundary-Scan instructions and associated data registers
support a standard methodology for accessing and
configuring Virtex-5 devices, complying with IEEE
standards 1149.1 and 1532.
Configuration
Virtex-5 devices are configured by loading the bitstream into
internal configuration memory using one of the following
modes:
Slave-serial mode
Master-serial mode
Slave SelectMAP mode
Master SelectMAP mode
Boundary-Scan mode (IEEE-1532 and -1149)
SPI mode (Serial Peripheral Interface standard Flash)
BPI-up/BPI-down modes (Byte-wide Peripheral
interface standard x8 or x16 NOR Flash)
In addition, Virtex-5 devices also support the following
configuration options:
256-bit AES bitstream decryption for IP protection
Multi-bitstream management (MBM) for cold/warm boot
support
Parallel configuration bus width auto-detection
Parallel daisy chain
Configuration CRC and ECC support for the most
robust, flexible device integrity checking
Virtex-5 device configuration is further discussed in the
Virtex-5 FPGA Configuration Guide.
System Monitor
FPGAs are an important building block in high
availability/reliability infrastructure. Therefore, there is need
to better monitor the on-chip physical environment of the
FPGA and its immediate surroundings within the system.
For the first time, the Virtex-5 family System Monitor
facilitates easier monitoring of the FPGA and its external
environment. Every member of the Virtex-5 family contains
a System Monitor block. The System Monitor is built around
a 10-bit 200kSPS ADC (Analog-to-Digital Converter). This
ADC is used to digitize a number of on-chip sensors to
provide information about the physical environment within
the FPGA. On-chip sensors include a temperature sensor
and power supply sensors. Access to the external
environment is provided via a number of external analog
input channels. These analog inputs are general purpose
and can be used to digitize a wide variety of voltage signal
types. Support for unipolar, bipolar, and true differential
input schemes is provided. There is full access to the on-
chip sensors and external channels via the JTAG TAP,
allowing the existing JTAG infrastructure on the PC board to
be used for analog test and advanced diagnostics during
development or after deployment in the field. The System
Monitor is fully operational after power up and before
configuration of the FPGA. System Monitor does not require
an explicit instantiation in a design to gain access to its
basic functionality. This allows the System Monitor to be
used even at a late stage in the design cycle.
The Virtex-5 FPGA System Monitor is further discussed in
theVirtex-5 FPGA System Monitor User Guide.
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參數(shù)描述 |
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| XC5VFX70T-1FF665C | 制造商:Xilinx 功能描述:FPGA VIRTEX-5 65NM 1V 665FCBGA - Trays 制造商:Xilinx 功能描述:IC FPGA VIRTEX5FX 70K 665-FCBGA |
| XC5VFX70T-1FF665CES | 功能描述:IC FPGA VIRTEX5FX 70K 665FCBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-5 FXT 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XC5VFX70T-1FF665I | 功能描述:IC FPGA VIRTEX-5FXT 665FFBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-5 FXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC5VFX70T-1FFG1136C | 功能描述:IC FPGA VIRTEX-5FX 70K 1136-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-5 FXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC5VFX70T-1FFG1136CES | 功能描述:IC FPGAVIRTEX5FX ES 70K 1136FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-5 FXT 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
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