參數(shù)資料
型號(hào): XC5VLX110-2FFG1153C
廠商: Xilinx Inc
文件頁(yè)數(shù): 44/91頁(yè)
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-5 110K 1153FBGA
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 LX
LAB/CLB數(shù): 8640
邏輯元件/單元數(shù): 110592
RAM 位總計(jì): 4718592
輸入/輸出數(shù): 800
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1153-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1153-FCBGA(35x35)
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML523-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
49
TDSPCCK_CEMM/TDSPCKC_CEMM
CEM input to M register CLK
0.25
0.18
0.29
0.21
0.36
0.26
ns
TDSPCCK_CEPP/TDSPCKC_CEPP
CEP input to P register CLK
0.56
0.01
0.63
0.01
0.73
0.01
ns
Setup and Hold Times of the RST Pins
TDSPCCK_{RSTAA, RSTBB}/
TDSPCKC_{RSTAA, RSTBB}
{RSTA, RSTB} input to {A, B} register
CLK
0.24
0.23
0.28
0.26
0.33
0.31
ns
TDSPCCK_RSTCC/ TDSPCKC_RSTCC
RSTC input to C register CLK
0.19
0.17
0.21
0.26
0.28
ns
TDSPCCK_RSTMM/ TDSPCKC_RSTMM
RSTM input to M register CLK
0.25
0.18
0.29
0.21
0.36
0.26
ns
TDSPCCK_RSTPP/TDSPCKC_RSTPP
RSTP input to P register CLK
0.56
0.01
0.63
0.01
0.73
0.01
ns
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_M
{A, B} input to {P, CARRYOUT} output
using multiplier
2.78
3.22
3.84
ns
TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_NM
{A, B} input to {P, CARRYOUT} output
not using multiplier
1.59
1.77
2.22
ns
TDSPDO_{CP, CCRYOUT, CRYINP, CRYINCRYOUT}
{C, CARRYIN} input to
{P, CARRYOUT} output
1.50
1.67
2.08
ns
Combinatorial Delays from Input Pins to Cascading Output Pins
TDSPDO_{AACOUT, BBCOUT}
{A, B} input to
{ACOUT, BCOUT} output
1.00
1.12
1.31
ns
TDSPDO_{APCOUT, ACRYCOUT, AMULTSIGNOUT,
BPCOUT, BCRYCOUT, BMULTSIGNOUT}_M
{A, B} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output using multiplier
2.78
3.22
3.84
ns
TDSPDO_{APCOUT, ACRYCOUT, AMULTSIGNOUT,
BPCOUT, BCRYCOUT, BMULTSIGNOUT}_NM
{A, B} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output not using multiplier
1.72
1.92
2.42
ns
TDSPDO_{CPCOUT, CCRYCOUT, CMULTSIGNOUT,
CRYINPCOUT, CRYINCRYCOUT,
CRYINMULTSIGNOUT}
{C, CARRYIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output
1.63
1.82
2.28
ns
Combinatorial Delays from Cascading Input Pins to All Output Pins
TDSPDO_{ACINP, ACINCRYOUT, BCINP,
BCINCRYOUT}_M
{ACIN, BCIN} input to {P, CARRYOUT}
output using multiplier
2.78
3.22
3.84
ns
TDSPDO_{ACINP, ACINCRYOUT, BCINP,
BCINCRYOUT}_NM
{ACIN, BCIN} input to {P, CARRYOUT}
output not using multiplier
1.59
1.77
2.22
ns
TDSPDO_{ACINACOUT, BCINBCOUT}
{ACIN, BCIN} input to {ACOUT, BCOUT}
output
1.00
1.12
1.31
ns
TDSPDO_{ACINPCOUT, ACINCRYCOUT,
ACINMULTSIGNOUT, BCINPCOUT, BCINCRYCOUT,
BCINMULTSIGNOUT}_M
{ACIN, BCIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output using multiplier
2.78
3.22
3.84
ns
TDSPDO_{ACINPCOUT, ACINCRYCOUT,
ACINMULTSIGNOUT, BCINPCOUT, BCINCRYCOUT,
BCINMULTSIGNOUT}_NM
{ACIN, BCIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output not using multiplier
1.72
1.92
2.42
ns
TDSPDO_{PCINP, CRYCINP, MULTSIGNINP,
PCINCRYOUT, CRYCINCRYOUT,
MULTSIGNINCRYOUT}
{PCIN, CARRYCASCIN, MULTSIGNIN}
input to {P, CARRYOUT} output
1.30
1.45
1.82
ns
Table 69: DSP48E Switching Characteristics (Cont’d)
Symbol
Description
Speed
Units
-3
-2
-1
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