Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
75
Table 94: Global Clock Setup and Hold With PLL in System-Synchronous Mode
Symbol
Description
Device
Speed Grade
Units
-3
-2
-1
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSPLL/ TPHPLL
No Delay Global Clock and IFF(2) with PLL in
System-Synchronous Mode
XC5VLX20T
N/A
1.74
–0.82
2.02
–0.82
ns
XC5VLX30
1.53
–0.80
1.68
–0.80
1.90
–0.79
ns
XC5VLX30T
1.52
–0.80
1.68
–0.80
1.90
–0.79
ns
XC5VLX50
1.50
–0.64
1.65
–0.63
1.89
–0.62
ns
XC5VLX50T
1.50
–0.64
1.65
–0.63
1.89
–0.62
ns
XC5VLX85
1.83
–0.63
1.95
–0.62
2.09
–0.61
ns
XC5VLX85T
1.83
–0.63
1.95
–0.62
2.09
–0.61
ns
XC5VLX110
1.83
–0.58
1.96
–0.57
2.10
–0.57
ns
XC5VLX110T
1.83
–0.58
1.96
–0.57
2.10
–0.57
ns
XC5VLX155
1.91
–0.49
2.09
–0.49
2.37
–0.47
ns
XC5VLX155T
1.91
–0.49
2.09
–0.49
2.37
–0.47
ns
XC5VLX220
N/A
1.93
–0.36
2.09
–0.36
ns
XC5VLX220T
N/A
1.93
–0.36
2.09
–0.36
ns
XC5VLX330
N/A
2.09
–0.21
2.33
–0.21
ns
XC5VLX330T
N/A
2.12
–0.21
2.34
–0.21
ns
XC5VSX35T
1.82
–0.82
2.02
–0.82
2.33
–0.82
ns
XC5VSX50T
1.96
–0.72
2.07
–0.72
2.20
–0.72
ns
XC5VSX95T
N/A
2.17
–0.80
2.35
–0.79
ns
XC5VSX240T
N/A
2.11
–0.14
2.33
–0.14
ns