• <li id="99ven"><form id="99ven"><xmp id="99ven"></xmp></form></li>
  • <big id="99ven"><form id="99ven"><label id="99ven"></label></form></big>
    <menuitem id="99ven"></menuitem>
  • <thead id="99ven"><wbr id="99ven"></wbr></thead>
    <code id="99ven"><input id="99ven"></input></code>
    參數(shù)資料
    型號: XC5VLX110-3FFG1153C
    廠商: Xilinx Inc
    文件頁數(shù): 14/91頁
    文件大?。?/td> 0K
    描述: IC FPGA VIRTEX-5 110K 1153FBGA
    標(biāo)準(zhǔn)包裝: 1
    系列: Virtex®-5 LX
    LAB/CLB數(shù): 8640
    邏輯元件/單元數(shù): 110592
    RAM 位總計(jì): 4718592
    輸入/輸出數(shù): 800
    電源電壓: 0.95 V ~ 1.05 V
    安裝類型: 表面貼裝
    工作溫度: 0°C ~ 85°C
    封裝/外殼: 1153-BBGA,F(xiàn)CBGA
    供應(yīng)商設(shè)備封裝: 1153-FCBGA(35x35)
    配用: 568-5088-ND - BOARD DEMO DAC1408D750
    HW-V5-ML523-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
    Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
    DS202 (v5.3) May 5, 2010
    Product Specification
    21
    Table 41 summarizes the DC specifications of the clock input of the GTX_DUAL tile. Figure 8 shows the single-ended input
    voltage swing. Figure 9 shows the peak-to-peak differential clock input voltage swing. Consult UG198: Virtex-5 FPGA
    RocketIO GTX Transceiver User Guide for further details.
    X-Ref Target - Figure 7
    Figure 7: Peak-to-Peak Differential Output Voltage
    Table 41: GTX_DUAL Tile Clock DC Input Level Specification(1)
    Symbol
    DC Parameter
    Conditions
    Min
    Typ
    Max
    Units
    VIDIFF
    Differential peak-to-peak input voltage
    210
    800
    2000
    mV
    VISE
    Single-ended input voltage
    105
    400
    1000
    mV
    RIN
    Differential input resistance
    90
    105
    130
    Ω
    CEXT
    Required external AC coupling capacitor
    100
    nF
    Notes:
    1.
    VMIN = 0V and VMAX = 1200mV
    X-Ref Target - Figure 8
    Figure 8: Single-Ended Clock Input Voltage Swing Peak-to-Peak
    X-Ref Target - Figure 9
    Figure 9: Differential Clock Input Voltage Swing Peak-to-Peak
    0
    +V
    –V
    P–N
    DVPPOUT
    ds202_02_081809
    0
    +V
    P
    N
    VISE
    ds202_03_052708
    0
    +V
    –V
    P – N
    VIDIFF
    ds202_04_052708
    相關(guān)PDF資料
    PDF描述
    IDT71V016SA12YG8 IC SRAM 1MBIT 12NS 44SOJ
    XC5VFX100T-2FFG1136C IC FPGA VIRTEX 5 100K 1136FFGBGA
    XC5VLX110-2FFG1760I IC FPGA VIRTEX-5 110K 1760FBGA
    XC5VLX110-2FFG1153I IC FPGA VIRTEX-5 110K 1153FBGA
    XC5VLX110-2FF1760I IC FPGA VIRTEX-5 110K 1760FBGA
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    XC5VLX110-3FFG1760C 功能描述:IC FPGA VIRTEX-5 110K 1760FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Virtex®-5 LX 標(biāo)準(zhǔn)包裝:24 系列:ECP2 LAB/CLB數(shù):1500 邏輯元件/單元數(shù):12000 RAM 位總計(jì):226304 輸入/輸出數(shù):131 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP(28x28)
    XC5VLX110-3FFG676C 功能描述:IC FPGA VIRTEX-5 110K 676FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Virtex®-5 LX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA(34.55x34.55)
    XC5VLX110T 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-5 Family Overview
    XC5VLX110T-1FF1136C 功能描述:IC FPGA VIRTEX-5 110K 1136FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Virtex®-5 LXT 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA(34.55x34.55)
    XC5VLX110T-1FF1136CES 制造商:Xilinx 功能描述: