參數(shù)資料
型號(hào): XC5VLX30-1FFG324CES
廠商: Xilinx Inc
文件頁數(shù): 22/91頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-5 ES 30K 324-FBGA
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 LX
LAB/CLB數(shù): 2400
邏輯元件/單元數(shù): 30720
RAM 位總計(jì): 1179648
輸入/輸出數(shù): 220
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 324-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 324-FCBGA(19x19)
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-AFX-FF324-500-G-ND - BOARD DEV VIRTEX 5 FF324
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
29
Dedicated Arithmetic Logic
DSP48E Quad 12-bit Adder/Subtracter
550
500
450
MHz
DSP48E Dual 24-bit Adder/Subtracter
550
500
450
MHz
DSP48E 48-bit Adder/Subtracter
550
500
450
MHz
DSP48E 48-bit Counter
550
500
450
MHz
DSP48E 48-bit Comparator
550
500
450
MHz
DSP48E 25 x 18 bit Pipelined Multiplier
550
500
450
MHz
DSP48E Direct 4-tap FIR Filter Pipelined
510
458
397
MHz
DSP48E Systolic n-tap FIR Filter Pipelined
550
500
450
MHz
Notes:
1.
Device used is the XC5VLX50T- FF1136
Table 53: Interface Performances
Description
Speed Grade
-3
-2
-1
Networking Applications
SFI-4.1 (SDR LVDS Interface)(1)
710 MHz
645 MHz
SPI-4.2 (DDR LVDS Interface)(2)
1.25 Gb/s
1.0 Gb/s
Memory Interfaces
DDR(3)
200 MHz
DDR2(4)
333 MHz
300 MHz
267 MHz
QDR II SRAM(5)
300 MHz
250 MHz
RLDRAM II(6)
333 MHz
300 MHz
250 MHz
Notes:
1.
Performance defined using design implementation described in application note XAPP856: SFI-4.1 16-Channel SDR Interface with Bus
Alignment
2.
Performance defined using design implementation described in application note XAPP860: 16-Channel, DDR LVDS Interface with Real-time
Window Monitoring
3.
Performance defined using design implementation described in application note XAPP851: DDR SDRAM Controller
4.
Performance defined using design implementation described in application note XAPP858: High-Performance DDR2 SDRAM Interface Data
Capture
5.
Performance defined using design implementation described in application note XAPP853: QDRII SRAM Interface
6.
Performance defined using design implementation described in application note XAPP852: Synthesizable RLDRAM II Controller
Table 52: Register-to-Register Performance (Cont’d)
Description
Register-to-Register (with I/O Delays)
Units
Speed Grade
-3
-2
-1
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XC5VLX30-1FFG324I 功能描述:IC FPGA VIRTEX-5 30K 324FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:Virtex®-5 LX 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC5VLX30-1FFG676C 功能描述:IC FPGA VIRTEX-5 30K 676FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:Virtex®-5 LX 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC5VLX30-1FFG676CES 功能描述:IC FPGA VIRTEX-5 ES 30K 676-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:Virtex®-5 LX 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA(31x31) 其它名稱:122-1789
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