參數(shù)資料
型號(hào): XC5VLX50-1FF324C
廠商: Xilinx Inc
文件頁(yè)數(shù): 73/91頁(yè)
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-5 50K 324FBGA
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 LX
LAB/CLB數(shù): 3600
邏輯元件/單元數(shù): 46080
RAM 位總計(jì): 1769472
輸入/輸出數(shù): 220
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 324-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 324-FCBGA(19x19)
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML561-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML550-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML521-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-AFX-FF324-500-G-ND - BOARD DEV VIRTEX 5 FF324
HW-V5GBE-DK-UNI-G-ND - KIT DEV V5 LXT GIGABIT ETHERNET
122-1508-ND - EVALUATION PLATFORM VIRTEX-5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
75
Table 94: Global Clock Setup and Hold With PLL in System-Synchronous Mode
Symbol
Description
Device
Speed Grade
Units
-3
-2
-1
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSPLL/ TPHPLL
No Delay Global Clock and IFF(2) with PLL in
System-Synchronous Mode
XC5VLX20T
N/A
1.74
–0.82
2.02
–0.82
ns
XC5VLX30
1.53
–0.80
1.68
–0.80
1.90
–0.79
ns
XC5VLX30T
1.52
–0.80
1.68
–0.80
1.90
–0.79
ns
XC5VLX50
1.50
–0.64
1.65
–0.63
1.89
–0.62
ns
XC5VLX50T
1.50
–0.64
1.65
–0.63
1.89
–0.62
ns
XC5VLX85
1.83
–0.63
1.95
–0.62
2.09
–0.61
ns
XC5VLX85T
1.83
–0.63
1.95
–0.62
2.09
–0.61
ns
XC5VLX110
1.83
–0.58
1.96
–0.57
2.10
–0.57
ns
XC5VLX110T
1.83
–0.58
1.96
–0.57
2.10
–0.57
ns
XC5VLX155
1.91
–0.49
2.09
–0.49
2.37
–0.47
ns
XC5VLX155T
1.91
–0.49
2.09
–0.49
2.37
–0.47
ns
XC5VLX220
N/A
1.93
–0.36
2.09
–0.36
ns
XC5VLX220T
N/A
1.93
–0.36
2.09
–0.36
ns
XC5VLX330
N/A
2.09
–0.21
2.33
–0.21
ns
XC5VLX330T
N/A
2.12
–0.21
2.34
–0.21
ns
XC5VSX35T
1.82
–0.82
2.02
–0.82
2.33
–0.82
ns
XC5VSX50T
1.96
–0.72
2.07
–0.72
2.20
–0.72
ns
XC5VSX95T
N/A
2.17
–0.80
2.35
–0.79
ns
XC5VSX240T
N/A
2.11
–0.14
2.33
–0.14
ns
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XC5VLX50-1FF324CES 制造商:Xilinx 功能描述:
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