參數(shù)資料
型號(hào): XC5VLX50-2FF1153C
廠商: Xilinx Inc
文件頁(yè)數(shù): 41/91頁(yè)
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-5 50K 1153FBGA
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 LX
LAB/CLB數(shù): 3600
邏輯元件/單元數(shù): 46080
RAM 位總計(jì): 1769472
輸入/輸出數(shù): 560
電源電壓: 0.95 V ~ 1.05 V
安裝類(lèi)型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1153-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1153-FCBGA(35x35)
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML561-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML550-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML521-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-AFX-FF1153-500-G-ND - BOARD DEV VIRTEX 5 FF1153
HW-V5GBE-DK-UNI-G-ND - KIT DEV V5 LXT GIGABIT ETHERNET
122-1508-ND - EVALUATION PLATFORM VIRTEX-5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
46
CLB Distributed RAM Switching Characteristics (SLICEM Only)
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 66: CLB Distributed RAM Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
Sequential Delays
TSHCKO
Clock to A – B outputs
1.08
1.26
1.54
ns, Max
TSHCKO_1
Clock to AMUX – BMUX outputs
1.19
1.38
1.68
ns, Max
Setup and Hold Times Before/After Clock CLK
TDS/TDH
A – D inputs to CLK
0.72
0.20
0.84
0.22
1.03
0.26
ns, Min
TAS/TAH
Address An inputs to clock
0.41
0.20
0.46
0.22
0.54
0.27
ns, Min
TWS/TWH
WE input to clock
0.34
–0.06
0.39
–0.04
0.46
–0.02
ns, Min
TCECK/TCKCE
CE input to CLK
0.36
–0.08
0.42
–0.07
0.51
–0.06
ns, Min
Clock CLK
TMPW
Minimum pulse width
0.70
0.82
1.00
ns, Min
TMCP
Minimum clock period
1.40
1.64
2.00
ns, Min
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
2.
TSHCKO also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path.
Table 67: CLB Shift Register Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
Sequential Delays
TREG
Clock to A – D outputs
1.23
1.43
1.73
ns,
Max
TREG_MUX
Clock to AMUX – DMUX output
1.33
1.55
1.87
ns,
Max
TREG_M31
Clock to DMUX output via M31 output
0.99
1.15
1.38
ns,
Max
Setup and Hold Times Before/After Clock CLK
TWS/TWH
WE input
0.21
–0.06
0.24
–0.04
0.29
–0.02
ns, Min
TCECK/TCKCE
CE input to CLK
0.23
–0.08
0.27
–0.07
0.33
–0.06
ns, Min
TDS/TDH
A – D inputs to CLK
0.57
0.07
0.66
0.09
0.78
0.11
ns, Min
Clock CLK
TMPW
Minimum pulse width
0.60
0.70
0.85
ns, Min
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
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