參數(shù)資料
型號: XC5VLX50-3FFG324C
廠商: Xilinx Inc
文件頁數(shù): 4/91頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-5 50K 324FBGA
標準包裝: 1
系列: Virtex®-5 LX
LAB/CLB數(shù): 3600
邏輯元件/單元數(shù): 46080
RAM 位總計: 1769472
輸入/輸出數(shù): 220
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 324-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 324-FCBGA(19x19)
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML561-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML550-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML521-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-AFX-FF324-500-G-ND - BOARD DEV VIRTEX 5 FF324
HW-V5GBE-DK-UNI-G-ND - KIT DEV V5 LXT GIGABIT ETHERNET
122-1508-ND - EVALUATION PLATFORM VIRTEX-5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
12
Table 21: Processor Block DCR Switching Characteristics
Clock Name
Description
Reference Clock
Speed Grade
Units
-3
-2
-1
Clock-to-out and setup relative to clock
TCK_CONTROL
CPMDCRCLK
TCK_ADDRESS
CPMDCRCLK
TCK_DATA
CPMDCRCLK
TCONTROL_CK
CPMDCRCLK
TADDRESS_CK
CPMDCRCLK
TDATA_CK
CPMDCRCLK
Table 22: Processor Block FCM Switching Characteristics
Clock Name
Description
Reference Clock
Speed Grade
Units
-3
-2
-1
Clock-to-out and setup relative to clock
TCK_CONTROL
CPMFCMCLK
0.967
1.084
1.324
ps
TCK_DATA
CPMFCMCLK
1.041
1.158
1.4
ps
TCK_INSTRUCTION
CPMFCMCLK
0.701
0.818
1.06
ps
TCONTROL_CK
CPMFCMCLK
1.057
1.218
1.395
ps
TDATA_CK
CPMFCMCLK
0.608
0.698
0.768
ps
TRESULT_CK
CPMFCMCLK
0.608
0.698
0.768
ps
Table 23: Processor Block MISC Switching Characteristics
Clock Name
Description
Reference Clock
Speed Grade
Units
-3
-2
-1
Clock-to-out and setup relative to clock
TCK_CONTROL
CLK1
TCK_ADDRESS
CLK2
TCK_DATA
CLK3
TCONTROL_CK
CLK4
TADDRESS_CK
CLK5
TDATA_CK
CLK6
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