參數(shù)資料
型號: XC5VLX85T-2FFG1136C
廠商: Xilinx Inc
文件頁數(shù): 58/91頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-5 85K 1136FBGA
產(chǎn)品變化通告: Step Intro and Pkg Change 11/March/2008
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 LXT
LAB/CLB數(shù): 6480
邏輯元件/單元數(shù): 82944
RAM 位總計: 3981312
輸入/輸出數(shù): 480
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1136-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1136-FCBGA
配用: 568-5088-ND - BOARD DEMO DAC1408D750
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
61
Table 81: Miscellaneous Timing Parameters
Symbol
Description
Speed Grade
-3
-2
-1
Units
Time Required to Achieve LOCK
TDLL_240
DLL output – Frequency range > 240 MHz (1)
80.00
s
TDLL_120_240
DLL output – Frequency range 120 - 240 MHz (1)
250.00
s
TDLL_60_120
DLL output – Frequency range 60 - 120 MHz (1)
900.00
s
TDLL_50_60
DLL output – Frequency range 50 - 60 MHz(1)
1300.00
s
TDLL_40_50
DLL output – Frequency range 40 - 50 MHz (1)
2000.00
s
TDLL_30_40
DLL output – Frequency range 30 - 40 MHz (1)
3600.00
s
TDLL_24_30
DLL output – Frequency range 24 - 30 MHz(1)
5000.00
s
TDLL_30
DLL output – Frequency range < 30 MHz (1)
5000.00
s
TFX_MIN
DFS outputs(2)
10.00
ms
TFX_MAX
10.00
ms
TDLL_FINE_SHIFT
Multiplication factor for DLL lock time with Fine Shift
2.00
Fine Phase Shifting
TRANGE_MS
Absolute shifting range in maximum speed mode
7.00
ns
TRANGE_MR
Absolute shifting range in maximum range mode
10.00
ns
Delay Lines
TTAP_MS_MIN
Tap delay resolution (Min) in maximum speed mode
7.00
ps
TTAP_MS_MAX
Tap delay resolution (Max) in maximum speed mode
30.00
ps
TTAP_MR_MIN
Tap delay resolution (Min) in maximum range mode
10.00
ps
TTAP_MR_MAX
Tap delay resolution (Max) in maximum range mode
40.00
ps
Notes:
1.
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
Table 82: Frequency Synthesis
Attribute
Min
Max
CLKFX_MULTIPLY
2
33
CLKFX_DIVIDE
1
32
Table 83: DCM Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
TDMCCK_PSEN/ TDMCKC_PSEN
PSEN Setup/Hold
1.20
0.00
1.35
0.00
1.56
0.00
ns
TDMCCK_PSINCDEC/ TDMCKC_PSINCDEC
PSINCDEC Setup/Hold
1.20
0.00
1.35
0.00
1.56
0.00
ns
TDMCKO_PSDONE
Clock to out of PSDONE
1.00
1.12
1.30
ns
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XC5VLX85T-2FFG1136CES 制造商:Xilinx 功能描述:
XC5VLX85T-2FFG1136I 功能描述:IC FPGA VIRTEX-5 85K 1136FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Virtex®-5 LXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC5VLX85T-3FF1136C 功能描述:IC FPGA VIRTEX-5 85K 1136FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Virtex®-5 LXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC5VLX85T-3FFG1136C 功能描述:IC FPGA VIRTEX-5 85K 1136FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Virtex®-5 LXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC5VLX85T-X1FF1136C 制造商:Xilinx 功能描述: