參數(shù)資料
型號: XC5VTX150T-2FF1156I
廠商: Xilinx Inc
文件頁數(shù): 15/91頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX5TXT 150K 1156FBGA
產(chǎn)品培訓(xùn)模塊: PCI Express and Virtex® -5 FPGAs
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 TXT
LAB/CLB數(shù): 11600
邏輯元件/單元數(shù): 148480
RAM 位總計: 8404992
輸入/輸出數(shù): 360
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1156-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1156-FCBGA
配用: 568-5088-ND - BOARD DEMO DAC1408D750
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
22
GTX_DUAL Tile Switching Characteristics
Consult UG198:Virtex-5 FPGA RocketIO GTX Transceiver User Guide for further information.
Table 42: GTX_DUAL Tile Performance
Symbol
Description
Speed Grade
Units
-3
-2
-1
FGTXMAX
Maximum GTX transceiver data rate
6.5
4.25
Gb/s
FGPLLMAX
Maximum PLL frequency
3.25
GHz
FGPLLMIN
Minimum PLL frequency
1.48
GHz
Table 43: Dynamic Reconfiguration Port (DRP) in the GTX_DUAL Tile Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
FGTXDRPCLK
GTX DCLK (DRP clock) maximum frequency
200
175
150
MHz
Table 44: GTX_DUAL Tile Reference Clock Switching Characteristics
Symbol
Description
Conditions
All Speed Grades
Units
Min
Typ
Max
FGCLK
Reference clock frequency range(1)
CLK
60
650
MHz
TRCLK
Reference clock rise time
20% – 80%
200
ps
TFCLK
Reference clock fall time
80% – 20%
200
ps
TDCREF
Reference clock duty cycle
CLK
40
50
60
%
TGJTT
Reference clock total jitter (2, 3)
At 100 KHz
–145
dBc/Hz
At 1 MHz
–150
dBc/Hz
TLOCK
Clock recovery frequency acquisition
time
Initial PLL lock
0.25
1
ms
TPHASE
Clock recovery phase acquisition time
Lock to data after PLL has
locked to the reference clock
200
s
Notes:
1.
GREFCLK can be used for serial bit rates up to 1 Gb/s; however, Jitter Specifications are not guaranteed when using GREFCLK.
2.
GTX_DUAL jitter characteristics measured using a clock with specification TGJTT. A reference clock with higher phase noise can be used
with link margin trade off.
3.
The selection of the reference clock is application dependent. This parameter describes the quality of the reference clock used during
transceiver jitter characterization - see Table 46 and Table 47.
X-Ref Target - Figure 10
Figure 10: Reference Clock Timing Parameters
ds202_05_100506
80%
20%
TFCLK
TRCLK
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