參數(shù)資料
型號(hào): XC6SLX16-3FTG256I
廠商: Xilinx Inc
文件頁(yè)數(shù): 4/11頁(yè)
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 6 14K 256FTGBGA
產(chǎn)品培訓(xùn)模塊: S6 Family Overview
標(biāo)準(zhǔn)包裝: 1
系列: Spartan® 6 LX
LAB/CLB數(shù): 1139
邏輯元件/單元數(shù): 14579
RAM 位總計(jì): 589824
輸入/輸出數(shù): 186
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA
其它名稱: 122-1730
XC6SLX16-3FTG256I-ND
Spartan-6 Family Overview
DS160 (v2.0) October 25, 2011
Product Specification
2
Spartan-6 FPGA Feature Summary
Table 1: Spartan-6 FPGA Feature Summary by Device
Device
Logic
Cells(1)
Configurable Logic Blocks (CLBs)
DSP48A1
Slices(3)
Block RAM Blocks
CMTs(5)
Memory
Controller
Blocks
(Max)(6)
Endpoint
Blocks for
PCI Express
Maximum
GTP
Transceivers
Total
I/O
Banks
Max
User
I/O
Slices(2)
Flip-Flops
Max
Distributed
RAM (Kb)
18 Kb(4)
Max (Kb)
XC6SLX4
3,840
600
4,800
75
8
12
216
2
0
4
132
XC6SLX9
9,152
1,430
11,440
90
16
32
576
2
0
4
200
XC6SLX16
14,579
2,278
18,224
136
32
576
2
0
4
232
XC6SLX25
24,051
3,758
30,064
229
38
52
936
2
0
4
266
XC6SLX45
43,661
6,822
54,576
401
58
116
2,088
4
2
0
4
358
XC6SLX75
74,637
11,662
93,296
692
132
172
3,096
6
4
0
6
408
XC6SLX100
101,261
15,822
126,576
976
180
268
4,824
6
4
0
6
480
XC6SLX150
147,443
23,038
184,304
1,355
180
268
4,824
6
4
0
6
576
XC6SLX25T
24,051
3,758
30,064
229
38
52
936
2
1
2
4
250
XC6SLX45T
43,661
6,822
54,576
401
58
116
2,088
4
2
1
4
296
XC6SLX75T
74,637
11,662
93,296
692
132
172
3,096
6
4
1
8
6
348
XC6SLX100T
101,261
15,822
126,576
976
180
268
4,824
6
4
1
8
6
498
XC6SLX150T
147,443
23,038
184,304
1,355
180
268
4,824
6
4
1
8
6
540
Notes:
1.
Spartan-6 FPGA logic cell ratings reflect the increased logic cell capability offered by the new 6-input LUT architecture.
2.
Each Spartan-6 FPGA slice contains four LUTs and eight flip-flops.
3.
Each DSP48A1 slice contains an 18 x 18 multiplier, an adder, and an accumulator.
4.
Block RAMs are fundamentally 18 Kb in size. Each block can also be used as two independent 9 Kb blocks.
5.
Each CMT contains two DCMs and one PLL.
6.
Memory Controller Blocks are not supported in the -3N speed grade.
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