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參數(shù)資料
| 型號(hào)： | XC6SLX4-2CPG196I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 11/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN 6 3K 196CPGBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Spartan® 6 LX |
| LAB/CLB數(shù)： | 300 |
| 邏輯元件/單元數(shù)： | 3840 |
| RAM 位總計(jì)： | 221184 |
| 輸入/輸出數(shù)： | 106 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 196-TFBGA，CSBGA |
| 供應(yīng)商設(shè)備封裝： | 196-CSBGA |
Spartan-6 Family Overview
DS160 (v2.0) October 25, 2011
Product Specification
9
Spartan-6 FPGA Ordering Information
Table 3 shows the speed and temperature grades available in the different Spartan-6 devices. Some devices might not be
available in every speed and temperature grade.
The Spartan-6 FPGA ordering information shown in Figure 1 applies to all packages, including Pb-Free. Refer to the
Package Marking section of UG385, Spartan-6 FPGA Packaging and Pinouts for a more detailed explanation of the device
markings.
Revision History
The following table shows the revision history for this document:
Table 3: Speed Grade and Temperature Ranges
Device Family
Speed Grade and Temperature Range
Commercial (C)
0°C to +85°C
Industrial (I)
–40°C to +100°C
Spartan-6 LX
-3, -3N, -2, -1L
Spartan-6 LXT
-3, -3N, -2
X-Ref Target - Figure 1
Figure 1: Spartan-6 FPGA Ordering Information
Date
Version
Description of Revisions
02/02/09
1.0
Initial Xilinx release.
05/05/09
1.1
Updated and simplified Designed for low cost, Multi-voltage, multi-standard SelectIO interface
banks, and Integrated Memory Controller blocks sections on page 1. Clarified PCI support on page 1is
only for the 33 MHz specification. Revised number of logic cells, slices, and maximum user I/O, and
the CSG225 package and the XC6SLX45T in the FGG676 package, added XC6SLX9 in the FT(G)256
package and XC6SLX45 in the CSG324 package, and added notes. Clerical edits to the following
and electrical characteristics in the Input/Output section.
06/24/09
1.2
XC6SLX75T devices. Added ordering information and FPGA documentation sections. Removed
partial reconfiguration discussion from the Readback section.
11/05/09
1.3
Updated Figure 1, page 9 to show -4 speed grade. Added 64-bit PCI support on page 1. Updated User
I/O numbers in Table 1and Table 2. Clarifying edits to these sections: Configuration, Digital Signal
Processing—DSP48A1 Slice, Input/Output, and PCI Express documentation.
Example: XC6SLX100T-2FGG676C
Device Type
Temperature Range:
C = Commercial (Tj = 0°C to +85°C)
I = Industrial (Tj = –40°C to +100°C)
Number of Pins
Package Type
Speed Grade
(-L1(1), -2, -3, -N3(2))
Pb-Free
DS160_01_011311
Note:
1) -L1 is the ordering code for the lower power, -1L speed grade.
Not all devices are offered in this version (LX only).
See the Spartan-6 FPGA data sheet for more information.
2) -N3 is the ordering code for the -3N speed grade,
which indicates the devices in which MCB functionality is not supported.
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