參數資料
| 型號： | XC6SLX75-L1FGG676I |
| 廠商： | Xilinx Inc |
| 文件頁數： | 9/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN 6 74K 676FGGBGA |
| 標準包裝： | 40 |
| 系列： | Spartan® 6 LX |
| LAB/CLB數： | 5831 |
| 邏輯元件/單元數： | 74637 |
| RAM 位總計： | 3170304 |
| 輸入/輸出數： | 408 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 676-BGA |
| 供應商設備封裝： | 676-FBGA（27x27） |
Spartan-6 Family Overview
DS160 (v2.0) October 25, 2011
Product Specification
7
Input/Output
The number of I/O pins varies from 102 to 576, depending on device and package size. Each I/O pin is configurable and can
comply with a large number of standards, using up to 3.3V. The Spartan-6 FPGA SelectIO Resources User Guide describes
the I/O compatibilities of the various I/O options. With the exception of supply pins and a few dedicated configuration pins,
all other package pins have the same I/O capabilities, constrained only by certain banking rules. All user I/O is bidirectional;
there are no input-only pins.
All I/O pins are organized in banks, with four banks on the smaller devices and six banks on the larger devices. Each bank
has several common VCCO output supply-voltage pins, which also powers certain input buffers. Some single-ended input
buffers require an externally applied reference voltage (VREF). There are several dual-purpose VREF-I/O pins in each bank.
In a given bank, when I/O standard calls for a VREF voltage, each VREF pin in that bank must be connected to the same
voltage rail and can not be used as an I/O pin.
I/O Electrical Characteristics
Single-ended outputs use a conventional CMOS push/pull output structure, driving High towards VCCO or Low towards
ground, and can be put into high-Z state. Many I/O features are available to the system designer to optionally invoke in each
I/O in their design, such as weak internal pull-up and pull-down resistors, strong internal split-termination input resistors,
adjustable output drive-strengths and slew-rates, and differential termination resistors. See the Spartan-6 FPGA SelectIO
Resources User Guide for more details on available options for each I/O standard.
I/O Logic
Input and Output Delay
This section describes the available logic resources connected to the I/O interfaces. All inputs and outputs can be configured
as either combinatorial or registered. Double data rate (DDR) is supported by all inputs and outputs. Any input or output can
be individually delayed by up to 256 increments (except in the -1L speed grade). This is implemented as IODELAY2. The
identical delay value is available either for data input or output. For a bidirectional data line, the transfer from input to output
delay is automatic. The number of delay steps can be set by configuration and can also be incremented or decremented
while in use.
Because these tap delays vary with supply voltage, process, and temperature, an optional calibration mechanism is built into
each IODELAY2:
For source synchronous designs where more accuracy is required, the calibration mechanism can (optionally)
determine dynamically how many taps are needed to delay data by one full I/O clock cycle, and then programs the
IODELAY2 with 50% of that value, thus centering the I/O clock in the middle of the data eye.
A special mode is available only for differential inputs, which uses a phase-detector mechanism to determine whether
the incoming data signal is being accurately sampled in the middle of the eye. The results from the phase-detector logic
can be used to either increment or decrement the input delay, one tap at a time, to ensure error-free operation at very
high bit rates.
ISERDES and OSERDES
Many applications combine high-speed bit-serial I/O with slower parallel operation inside the device. This requires a
serializer and deserializer (SerDes) inside the I/O structure. Each input has access to its own deserializer (serial-to-parallel
converter) with programmable parallel width of 2, 3, or 4 bits. Where differential inputs are used, the two serializers can be
cascaded to provide parallel widths of 5, 6, 7, or 8 bits. Each output has access to its own serializer (parallel-to-serial
converter) with programmable parallel width of 2, 3, or 4 bits. Two serializers can be cascaded when a differential driver is
used to give access to bus widths of 5, 6, 7, or 8 bits.
When distributing a double data rate clock, all SerDes data is actually clocked in/out at single data rate to eliminate the
possibility of bit errors due to duty cycle distortion. This faster single data rate clock is either derived via frequency
multiplication in a PLL, or doubled locally in each IOB by differentiating both clock edges when the incoming clock uses
double data rate.
相關PDF資料 |
PDF描述 |
|---|---|
| XC6SLX75T-N3FGG676C | IC FPGA SPARTAN-6 676FBGA |
| 93AA76/SN | IC EEPROM 8KBIT 3MHZ 8SOIC |
| 93AA76T/SN | IC EEPROM 8KBIT 3MHZ 8SOIC |
| 93LC86/SN | IC EEPROM 16KBIT 3MHZ 8SOIC |
| XC6SLX75T-2FGG676C | IC FPGA SPARTAN 6 74K 676FGGBGA |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XC6SLX75-N3CSG484C | 功能描述:IC FPGA SPARTAN-6 484CSBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:Spartan® 6 LX 產品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數:4080 邏輯元件/單元數:52224 RAM 位總計:4866048 輸入/輸出數:480 門數:- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，FCBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC6SLX75-N3CSG484I | 功能描述:IC FPGA SPARTAN-6 484CSBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:Spartan® 6 LX 產品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數:4080 邏輯元件/單元數:52224 RAM 位總計:4866048 輸入/輸出數:480 門數:- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，FCBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC6SLX75-N3FG484C | 制造商:Xilinx 功能描述:IC FPGA 280 I/O 484FBGA 制造商:Xilinx 功能描述:IC FPGA SPARTAN 6 75K 484BGA |
| XC6SLX75-N3FG484I | 制造商:Xilinx 功能描述:IC FPGA SPARTAN 6 75K 484BGA |
| XC6SLX75-N3FG676C | 制造商:Xilinx 功能描述:IC FPGA 408 I/O 676FCBGA 制造商:Xilinx 功能描述:IC FPGA SPARTAN 6 75K 676BGA |
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