參數(shù)資料
型號: XC6VCX130T-1FFG784C
廠商: Xilinx Inc
文件頁數(shù): 19/52頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX 6 128K 784FFGBGA
產(chǎn)品培訓模塊: Virtex-6 FPGA Overview
產(chǎn)品變化通告: Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標準包裝: 1
系列: Virtex® 6 CXT
LAB/CLB數(shù): 10000
邏輯元件/單元數(shù): 128000
RAM 位總計: 9732096
輸入/輸出數(shù): 400
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 784-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 784-FCBGA
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
26
IOB Pad Input/Output/3-State Switching Characteristics
Table 38 summarizes the values of standard-specific data
input delay adjustments, output delays terminating at pads
(based on standard) and 3-state delays.
TIOPI is described as the delay from IOB pad through the
input buffer to the I-pin of an IOB pad. The delay varies
depending on the capability of the SelectIO input buffer.
TIOOP is described as the delay from the O pin to the IOB
pad through the output buffer of an IOB pad. The delay
varies depending on the capability of the SelectIO output
buffer.
TIOTP is described as the delay from the T pin to the IOB
pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO
capability of the output buffer.
Table 39 summarizes the value of TIOTPHZ. TIOTPHZ is
described as the delay from the T pin to the IOB pad
through the output buffer of an IOB pad, when 3-state is
enabled (i.e., a high impedance state).
Table 38: IOB Switching Characteristics
I/O Standard
TIOPI
TIOOP
TIOTP
Units
Speed Grade
-2
-1
-2
-1
-2
-1
LVDS_25
1.09
1.68
ns
LVDSEXT_25
1.09
1.84
ns
HT_25
1.09
1.78
ns
BLVDS_25
1.09
1.67
ns
RSDS_25 (point to point)
1.09
1.68
ns
HSTL_I
1.06
1.73
ns
HSTL_II
1.06
1.74
ns
HSTL_III
1.06
1.71
ns
HSTL_I_18
1.06
1.75
ns
HSTL_II_18
1.06
1.81
ns
HSTL_III_18
1.06
1.71
ns
SSTL2_I
1.06
1.77
ns
SSTL2_II
1.06
1.72
ns
SSTL15
1.06
1.71
ns
LVCMOS25, Slow, 2 mA
0.66
6.01
ns
LVCMOS25, Slow, 4 mA
0.66
3.79
ns
LVCMOS25, Slow, 6 mA
0.66
3.08
ns
LVCMOS25, Slow, 8 mA
0.66
2.72
ns
LVCMOS25, Slow, 12 mA
0.66
2.17
ns
LVCMOS25, Slow, 16 mA
0.66
2.29
ns
LVCMOS25, Slow, 24 mA
0.66
2.02
ns
LVCMOS25, Fast, 2 mA
0.66
6.04
ns
LVCMOS25, Fast, 4 mA
0.66
3.82
ns
LVCMOS25, Fast, 6 mA
0.66
2.99
ns
LVCMOS25, Fast, 8 mA
0.66
2.65
ns
LVCMOS25, Fast, 12 mA
0.66
2.08
ns
LVCMOS25, Fast, 16 mA
0.66
2.13
ns
LVCMOS25, Fast, 24 mA
0.66
1.99
ns
相關(guān)PDF資料
PDF描述
XC5VLX50T-2FFG665C IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-2FF665C IC FPGA VIRTEX-5 50K 665FCBGA
XC5VFX30T-1FF665I IC FPGA VIRTEX-5FXT 665FFBGA
BR93L46RF-WE2 IC EEPROM 1KBIT 2MHZ 8SOP
AGM40DTAH-S189 CONN EDGECARD 80POS R/A .156 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC6VCX130T-1FFG784I 功能描述:IC FPGA VIRTEX 6 128K 784FFGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Virtex® 6 CXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC6VCX130T-2FF1156C 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 128000 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA 600 I/O 1156FCBGA 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 128K 1156BGA
XC6VCX130T-2FF1156I 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 128000 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA 600 I/O 1156FCBGA
XC6VCX130T-2FF484C 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 128000 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA 240 I/O 484FCBGA
XC6VCX130T-2FF484I 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 128000 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA 240 I/O 484FCBGA 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 128K 484BGA