參數(shù)資料
型號(hào)： XC6VCX130T-1FFG784I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 28/52頁(yè)
文件大?。?/td> 0K
描述： IC FPGA VIRTEX 6 128K 784FFGBGA
產(chǎn)品培訓(xùn)模塊： Virtex-6 FPGA Overview
產(chǎn)品變化通告： Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標(biāo)準(zhǔn)包裝： 1
系列： Virtex® 6 CXT
LAB/CLB數(shù)： 10000
邏輯元件/單元數(shù)： 128000
RAM 位總計(jì)： 9732096
輸入/輸出數(shù)： 400
電源電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 784-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 784-FCBGA
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
34
Input/Output Delay Switching Characteristics
CLB Switching Characteristics
Table 46: Input/Output Delay Switching Characteristics
Symbol
Description
Speed Grade
Units
-2
-1
IDELAYCTRL
TDLYCCO_RDY
Reset to Ready for IDELAYCTRL
3
s
FIDELAYCTRL_REF
REFCLK frequency
200
MHz
IDELAYCTRL_REF_PRECISION REFCLK precision
±10
MHz
TIDELAYCTRL_RPW
Minimum Reset pulse width
50
ns
IODELAY
TIDELAYRESOLUTION
IODELAY Chain Delay Resolution
1/(32 x 2 x FREF)
ps
TIDELAYPAT_JIT
Pattern dependent period jitter in delay chain for clock
pattern.(1)
00
ps
per tap
Pattern dependent period jitter in delay chain for
random data pattern.(2)
±5
ps
per tap
Pattern dependent period jitter in delay chain for
random data pattern.(3)
±9
ps
per tap
TIODELAY_CLK_MAX
Maximum frequency of CLK input to IODELAY
300
MHz
TIODCCK_CE / TIODCKC_CE
CE pin Setup/Hold with respect to CK
0.65/–0.09
ns
TIODCK_INC/ TIODCKC_INC
INC pin Setup/Hold with respect to CK
0.31/–0.00
ns
TIODCCK_RST/ TIODCKC_RST
RST pin Setup/Hold with respect to CK
0.69/–0.08
ns
TIODDO_T
TSCONTROL delay to MUXE/MUXF switching and
through IODELAY
Note 4
ps
TIODDO_IDATAIN
Propagation delay through IODELAY
Note 4
ps
TIODDO_ODATAIN
Propagation delay through IODELAY
Note 4
ps
Notes:
1.
When HIGH_PERFORMANCE mode is set to TRUE or FALSE.
2.
When HIGH_PERFORMANCE mode is set to TRUE
3.
When HIGH_PERFORMANCE mode is set to FALSE.
4.
Delay depends on IODELAY tap setting. See the TRACE report for actual values.
Table 47: CLB Switching Characteristics
Symbol
Description
Speed Grade
Units
-2
-1
Combinatorial Delays
TILO
An – Dn LUT address to A
0.08
ns, Max
An – Dn LUT address to AMUX/CMUX
0.23
0.25
ns, Max
An – Dn LUT address to BMUX_A
0.37
0.41
ns, Max
TITO
An – Dn inputs to A – D Q outputs
0.79
0.91
ns, Max
TAXA
AX inputs to AMUX output
0.42
0.48
ns, Max
TAXB
AX inputs to BMUX output
0.47
0.53
ns, Max
TAXC
AX inputs to CMUX output
0.52
0.60
ns, Max
TAXD
AX inputs to DMUX output
0.55
0.63
ns, Max
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