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參數(shù)資料
型號： XC6VCX130T-2FFG1156C
廠商： Xilinx Inc
文件頁數(shù)： 41/52頁
文件大?。?/td> 0K
描述： IC FPGA VIRTEX 6 128K 1156FFGBGA
產(chǎn)品培訓模塊： Virtex-6 FPGA Overview
產(chǎn)品變化通告： Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標準包裝： 1
系列： Virtex® 6 CXT
LAB/CLB數(shù)： 10000
邏輯元件/單元數(shù)： 128000
RAM 位總計： 9732096
輸入/輸出數(shù)： 600
電源電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 1156-BBGA，F(xiàn)CBGA
供應商設(shè)備封裝： 1156-FCBGA（35x35）
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
46
TSTATPHAOFFSET
Static Phase Offset of the MMCM Outputs(3)
0.12
ns
TOUTJITTER
MMCM Output Jitter(4)
Note 1
TOUTDUTY
MMCM Output Clock Duty Cycle Precision(5)
0.20
ns
TLOCKMAX
MMCM Maximum Lock Time
100
s
FOUTMAX
MMCM Maximum Output Frequency
700
MHz
FOUTMIN
MMCM Minimum Output Frequency(6)(7)
4.69
MHz
TEXTFDVAR
External Clock Feedback Variation
< 20% of clock input period or 1 ns
Max
RSTMINPULSE
Minimum Reset Pulse Width
1.5
ns
FPFDMAX
Maximum Frequency at the Phase Frequency Detector
with Bandwidth Set to High or Optimized(8)
450
MHz
Maximum Frequency at the Phase Frequency Detector
with Bandwidth Set to Low
300
MHz
FPFDMIN
Minimum Frequency at the Phase Frequency Detector
with Bandwidth Set to High or Optimized
135
MHz
Minimum Frequency at the Phase Frequency Detector
with Bandwidth Set to Low
10.00
MHz
TFBDELAY
Maximum Delay in the Feedback Path
3 ns Max or one CLKIN cycle
TMMCMDCK_PSEN/
TMMCMCKD_PSEN
Setup and Hold of Phase Shift Enable
1.04/0.00
ns
TMMCMDCK_PSINCDEC/
TMMCMCKD_PSINCDEC
Setup and Hold of Phase Shift Increment/Decrement
1.04/0.00
ns
TMMCMCKO_PSDONE
Phase Shift Clock-to-Out of PSDONE
0.38
ns
Notes:
1.
When DIVCLK_DIVIDE = 3 or 4, FINMAX is 315 MHz.
2.
The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
3.
The static offset is measured between any MMCM outputs with identical phase.
4.
Values for this parameter are available in the Architecture Wizard.
5.
Includes global clock buffer.
6.
Calculated as FVCO/128 assuming output duty cycle is 50%.
7.
When CASCADE4_OUT = TRUE, FOUTMIN is 0.036 MHz.
8.
In ISE software 12.3 (or earlier versions supporting the Virtex-6 family), the phase frequency detector Optimized bandwidth setting is
equivalent to the High bandwidth setting. Starting with ISE software 12.4, the Optimized bandwidth setting is automatically adjusted to Low
when the software can determine that the phase frequency detector input is less than 135 MHz.
Table 57: MMCM Specification (Cont’d)
Symbol
Description
Speed Grade
Units
-2
-1
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XC6VCX130T-2FFG1156I 功能描述:IC FPGA VIRTEX 6 128K 1156FFGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 6 CXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
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