參數(shù)資料
型號(hào): XC6VCX195T-1FFG784C
廠商: Xilinx Inc
文件頁數(shù): 30/52頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX 6 199K 784FFGBGA
產(chǎn)品培訓(xùn)模塊: Virtex-6 FPGA Overview
產(chǎn)品變化通告: Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標(biāo)準(zhǔn)包裝: 1
系列: Virtex® 6 CXT
LAB/CLB數(shù): 15600
邏輯元件/單元數(shù): 199680
RAM 位總計(jì): 12681216
輸入/輸出數(shù): 400
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 784-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 784-FCBGA
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
36
CLB Distributed RAM Switching Characteristics (SLICEM Only)
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 48: CLB Distributed RAM Switching Characteristics
Symbol
Description
Speed Grade
Units
-2
-1
Sequential Delays
TSHCKO
Clock to A – B outputs
1.36
1.56
ns, Max
TSHCKO_1
Clock to AMUX – BMUX outputs
1.71
1.96
ns, Max
Setup and Hold Times Before/After Clock CLK
TDS/TDH
A – D inputs to CLK
0.88/0.22
1.01/0.26
ns, Min
TAS/TAH
Address An inputs to clock
0.27/0.70
0.31/0.80
ns, Min
TWS/TWH
WE input to clock
0.40/–0.01
0.46/0.00
ns, Min
TCECK/TCKCE
CE input to CLK
0.41/–0.02
0.48/–0.01
ns, Min
Clock CLK
TMPW
Minimum pulse width
1.00
1.15
ns, Min
TMCP
Minimum clock period
2.00
2.30
ns, Min
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
2.
TSHCKO also represents the CLK to XMUX output. Refer to the TRACE report for the CLK to XMUX path.
Table 49: CLB Shift Register Switching Characteristics
Symbol
Description
Speed Grade
Units
-2
-1
Sequential Delays
TREG
Clock to A – D outputs
1.58
1.82
ns, Max
TREG_MUX
Clock to AMUX – DMUX output
1.93
2.22
ns, Max
TREG_M31
Clock to DMUX output via M31 output
1.55
1.78
ns, Max
Setup and Hold Times Before/After Clock CLK
TWS/TWH
WE input
0.09/–0.01
0.10/0.00
ns, Min
TCECK/TCKCE
CE input to CLK
0.10/–0.02
0.11/–0.01
ns, Min
TDS/TDH
A – D inputs to CLK
0.94/0.24
1.08/0.28
ns, Min
Clock CLK
TMPW
Minimum pulse width
0.85
0.98
ns, Min
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
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XC6VCX195T-1FFG784I 功能描述:IC FPGA VIRTEX 6 199K 784FFGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Virtex® 6 CXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC6VCX195T-2FF1156C 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 199680 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA 600 I/O 1156FCBGA
XC6VCX195T-2FF1156I 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 199680 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA 600 I/O 1156FCBGA
XC6VCX195T-2FF784C 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 199680 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 195K 784BGA
XC6VCX195T-2FF784I 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 199680 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 195K 784BGA 制造商:Xilinx 功能描述:IC FPGA 400 I/O 784FCBGA