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  • 參數(shù)資料
    型號: XC6VCX195T-2FFG1156I
    廠商: Xilinx Inc
    文件頁數(shù): 46/52頁
    文件大?。?/td> 0K
    描述: IC FPGA VIRTEX 6 199K 1156FFGBGA
    產(chǎn)品培訓(xùn)模塊: Virtex-6 FPGA Overview
    產(chǎn)品變化通告: Virtex-6 FIFO Input Logic Reset 18/Apr/2011
    標(biāo)準(zhǔn)包裝: 1
    系列: Virtex® 6 CXT
    LAB/CLB數(shù): 15600
    邏輯元件/單元數(shù): 199680
    RAM 位總計: 12681216
    輸入/輸出數(shù): 600
    電源電壓: 0.95 V ~ 1.05 V
    安裝類型: 表面貼裝
    工作溫度: -40°C ~ 100°C
    封裝/外殼: 1156-BBGA,F(xiàn)CBGA
    供應(yīng)商設(shè)備封裝: 1156-FCBGA(35x35)
    Virtex-6 CXT Family Data Sheet
    DS153 (v1.6) February 11, 2011
    Product Specification
    50
    Revision History
    The following table shows the revision history for this document:
    Table 66: Sample Window
    Symbol
    Description
    Device
    Speed Grade
    Units
    -2
    -1
    TSAMP
    Sampling Error at Receiver Pins(1)
    All
    610
    ps
    TSAMP_BUFIO
    Sampling Error at Receiver Pins using BUFIO(2)
    All
    400
    ps
    Notes:
    1.
    This parameter indicates the total sampling error of Virtex-6 CXT FPGA DDR input registers, measured across voltage, temperature, and
    process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements
    include:
    - CLK0 MMCM jitter
    - MMCM accuracy (phase offset)
    - MMCM phase shift resolution
    These measurements do not include package or clock tree skew.
    2.
    This parameter indicates the total sampling error of Virtex-6 CXT FPGA DDR input registers, measured across voltage, temperature, and
    process. The characterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers’ edges of
    operation. These measurements do not include package or clock tree skew.
    Table 67: Pin-to-Pin Setup/Hold and Clock-to-Out
    Symbol
    Description
    Speed Grade
    Units
    -2
    -1
    Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
    TPSCS/TPHCS
    Setup/Hold of I/O clock
    –0.33/1.31
    ns
    Pin-to-Pin Clock-to-Out Using BUFIO
    TICKOFCS
    Clock-to-Out of I/O clock
    5.19
    ns
    Date
    Version
    Description of Revisions
    07/08/09
    1.0
    Initial Xilinx release.
    02/05/10
    1.1
    Removed Figure 11: Placement Diagram for the FF1156 Package (5 of 5) from page 11 as there are
    only 16 GTX transceivers in the FF1156 package. Corrected the placement diagrams in Figure 2
    through Figure 10.
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