參數(shù)資料
型號(hào)： XC6VCX195T-2FFG784C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 26/52頁(yè)
文件大?。?/td> 0K
描述： IC FPGA VIRTEX 6 199K 784FFGBGA
產(chǎn)品培訓(xùn)模塊： Virtex-6 FPGA Overview
產(chǎn)品變化通告： Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標(biāo)準(zhǔn)包裝： 1
系列： Virtex® 6 CXT
LAB/CLB數(shù)： 15600
邏輯元件/單元數(shù)： 199680
RAM 位總計(jì)： 12681216
輸入/輸出數(shù)： 400
電源電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 784-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 784-FCBGA
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
32
Input Serializer/Deserializer Switching Characteristics
Table 43: OLOGIC Switching Characteristics
Symbol
Description
Speed Grade
Units
-2
-1
Setup/Hold
TODCK/TOCKD
D1/D2 pins Setup/Hold with respect to CLK
0.54/–0.11
ns
TOOCECK/TOCKOCE
OCE pin Setup/Hold with respect to CLK
0.22/–0.05
ns
TOSRCK/TOCKSR
SR pin Setup/Hold with respect to CLK
0.71/–0.29
ns
TOTCK/TOCKT
T1/T2 pins Setup/Hold with respect to CLK
0.56/–0.10
ns
TOTCECK/TOCKTCE
TCE pin Setup/Hold with respect to CLK
0.21/–0.05
ns
Combinatorial
TDOQ
D1 to OQ out or T1 to TQ out
1.01
ns
Sequential Delays
TOCKQ
CLK to OQ/TQ out
0.71
ns
TRQ
SR pin to OQ/TQ out
1.05
ns
TGSRQ
Global Set/Reset to Q outputs
10.51
ns
Set/Reset
TRPW
Minimum Pulse Width, SR inputs
1.20
ns, Min
Table 44: ISERDES Switching Characteristics
Symbol
Description
Speed Grade
Units
-2
-1
Setup/Hold for Control Lines
TISCCK_BITSLIP/ TISCKC_BITSLIP
BITSLIP pin Setup/Hold with respect to CLKDIV
0.09/0.17
ns
TISCCK_CE / TISCKC_CE(2)
CE pin Setup/Hold with respect to CLK (for CE1)
0.27/0.04
ns
TISCCK_CE2 / TISCKC_CE2(2)
CE pin Setup/Hold with respect to CLKDIV (for CE2)
–0.06/0.31
ns
Setup/Hold for Data Lines
TISDCK_D /TISCKD_D
D pin Setup/Hold with respect to CLK
0.09/0.11
ns
TISDCK_DDLY /TISCKD_DDLY
DDLY pin Setup/Hold with respect to CLK (using
IODELAY)(1)
0.14/0.07
ns
TISDCK_D_DDR /TISCKD_D_DDR
D pin Setup/Hold with respect to CLK at DDR mode
0.09/0.11
ns
TISDCK_DDLY_DDR
TISCKD_DDLY_DDR
D pin Setup/Hold with respect to CLK at DDR mode
(using IODELAY)(1)
0.14/0.07
ns
Sequential Delays
TISCKO_Q
CLKDIV to out at Q pin
0.75
ns
Propagation Delays
TISDO_DO
D input to DO output pin
0.25
ns
Notes:
1.
Recorded at 0 tap value.
2.
TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in a TRACE report.
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參數(shù)描述
XC6VCX195T-2FFG784I 功能描述:IC FPGA VIRTEX 6 199K 784FFGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex® 6 CXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC6VCX240T 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-6 CXT Family Data Sheet
XC6VCX240T-1FF1156C 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 241152 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA 600 I/O 1156FCBGA
XC6VCX240T-1FF1156I 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 241152 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 240K 1156BGA 制造商:Xilinx 功能描述:IC FPGA 600 I/O 1156FCBGA
XC6VCX240T-1FF784C 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 241152 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 240K 784BGA
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