F
參數(shù)資料
型號： XC6VCX240T-1FFG1156I
廠商： Xilinx Inc
文件頁數(shù)： 32/52頁
文件大?。?/td> 0K
描述： IC FPGA VIRTEX 6 241K 1156FFGBGA
產(chǎn)品培訓模塊： Virtex-6 FPGA Overview
產(chǎn)品變化通告： Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標準包裝： 1
系列： Virtex® 6 CXT
LAB/CLB數(shù)： 18840
邏輯元件/單元數(shù)： 241152
RAM 位總計： 15335424
輸入/輸出數(shù)： 600
電源電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 1156-BBGA，F(xiàn)CBGA
供應商設備封裝： 1156-FCBGA（35x35）
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
38
Maximum Frequency
FMAX
Block RAM
(Write First and No Change modes)
400
350
MHz
Block RAM (Read First mode)
400
347
MHz
Block RAM (SDP mode)(12)
400
347
MHz
FMAX_CASCADE
Block RAM Cascade
(Write First and No Change modes)
400
347
MHz
Block RAM Cascade (Read First mode)
350
304
MHz
FMAX_FIFO
FIFO in all modes
400
350
MHz
FMAX_ECC
Block RAM and FIFO in ECC configuration
325
282
MHz
Notes:
1.
TRACE will report all of these parameters as TRCKO_DO.
2.
TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters.
3.
These parameters also apply to synchronous FIFO with DO_REG = 0.
4.
TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters.
5.
These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
6.
TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR.
7.
TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT.
8.
The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is
possible.
9.
TRCKO_DI includes both A and B inputs as well as the parity inputs of A and B.
10. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
11. The FIFO reset must be asserted for at least three positive clock edges.
12. When using ISE software v12.4 or later, if the RDARRDR_COLLISION_HWCONFIG attribute is set to PERFORMANCE or the block RAM
is in single-port operation, then the faster FMAX for WRITE_FIRST/NO_CHANGE modes apply.
Table 50: Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol
Description
Speed Grade
Units
-2
-1
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XC6VCX240T-1FFG784C 功能描述:IC FPGA VIRTEX 6 241K 784FFGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 6 CXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
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