參數(shù)資料
型號: XC6VCX75T-1FFG484C
廠商: Xilinx Inc
文件頁數(shù): 16/52頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX 6 74K 484FFGBGA
產(chǎn)品培訓(xùn)模塊: Virtex-6 FPGA Overview
產(chǎn)品變化通告: Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標(biāo)準(zhǔn)包裝: 1
系列: Virtex® 6 CXT
LAB/CLB數(shù): 5820
邏輯元件/單元數(shù): 74496
RAM 位總計(jì): 5750784
輸入/輸出數(shù): 240
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 484-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 484-FCBGA
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
23
Ethernet MAC Switching Characteristics
Consult Virtex-6 FPGA Embedded Tri-mode Ethernet MAC User Guide for further information.
Integrated Interface Block for PCI Express Designs Switching Characteristics
More information and documentation on solutions for PCI Express designs can be found at:
Table 33: Maximum Ethernet MAC Performance
Symbol
Description
Conditions
Speed Grade
Units
-2
-1
FTEMACCLIENT
Client interface maximum frequency
10 Mb/s – 8-bit width
2.5(1)
MHz
100 Mb/s – 8-bit width
25(2)
MHz
1000 Mb/s – 8-bit width
125
MHz
1000 Mb/s – 16-bit width
62.5
MHz
FTEMACPHY
Physical interface maximum frequency
10 Mb/s – 4-bit width
2.5
MHz
100 Mb/s – 4-bit width
25
MHz
1000 Mb/s – 8-bit width
125
MHz
Notes:
1.
When not using clock enable, the FMAX is lowered to 1.25 MHz.
2.
When not using clock enable, the FMAX is lowered to 12.5 MHz.
Table 34: Maximum Performance for PCI Express Designs
Symbol
Description
Speed Grade
Units
-2
-1
FPIPECLK
Pipe clock maximum frequency
125
MHz
FUSERCLK
User clock maximum frequency
250
MHz
FDRPCLK
DRP clock maximum frequency
250
MHz
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