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參數(shù)資料
| 型號： | XC6VHX255T-3FFG1923C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA VIRTEX 1924FCBGA |
| 產(chǎn)品培訓模塊： | Virtex-6 FPGA Overview |
| 產(chǎn)品變化通告： | Virtex-6 FIFO Input Logic Reset 18/Apr/2011 |
| 標準包裝： | 12 |
| 系列： | Virtex® 6 HXT |
| LAB/CLB數(shù)： | 19800 |
| 邏輯元件/單元數(shù)： | 253440 |
| RAM 位總計： | 19021824 |
| 輸入/輸出數(shù)： | 480 |
| 電源電壓： | 0.95 V ~ 1.05 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 1924-BBGA，F(xiàn)CBGA |
| 供應商設備封裝： | 1924-FCBGA |
Virtex-6 Family Overview
DS150 (v2.4) January 19, 2012
Product Specification
2
Virtex-6 FPGA Feature Summary
Table 1: Virtex-6 FPGA Feature Summary by Device
Device
Logic
Cells
Configurable Logic
Blocks (CLBs)
DSP48E1
Slices(2)
Block RAM Blocks
MMCMs(4)
Interface
Blocks for
PCI Express
Ethernet
MACs(5)
Maximum
Transceivers
Total
I/O
Banks(6)
Max
User
I/O(7)
Slices(1)
Max
Distributed
RAM (Kb)
18 Kb(3) 36 Kb
Max
(Kb)
GTX
GTH
XC6VLX75T
74,496
11,640
1,045
288
312
156
5,616
6
1
4
12
0
9
360
XC6VLX130T
128,000
20,000
1,740
480
528
264
9,504
10
2
4
20
0
15
600
XC6VLX195T
199,680
31,200
3,040
640
688
344
12,384
10
2
4
20
0
15
600
XC6VLX240T
241,152
37,680
3,650
768
832
416
14,976
12
2
4
24
0
18
720
XC6VLX365T
364,032
56,880
4,130
576
832
416
14,976
12
2
4
24
0
18
720
XC6VLX550T
549,888
85,920
6,200
864
1,264
632
22,752
18
2
4
36
0
30
1200
XC6VLX760
758,784
118,560
8,280
864
1,440
720
25,920
18
0
30
1200
XC6VSX315T 314,880
49,200
5,090
1,344
1,408
704
25,344
12
2
4
24
0
18
720
XC6VSX475T 476,160
74,400
7,640
2,016
2,128
1,064 38,304
18
2
4
36
0
21
840
XC6VHX250T 251,904
39,360
3,040
576
1,008
504
18,144
12
4
48
0
8
320
XC6VHX255T 253,440
39,600
3,050
576
1,032
516
18,576
12
2
24
12
480
XC6VHX380T 382,464
59,760
4,570
864
1,536
768
27,648
18
4
48
24
18
720
XC6VHX565T 566,784
88,560
6,370
864
1,824
912
32,832
18
4
48
24
18
720
Notes:
1.
Each Virtex-6 FPGA slice contains four LUTs and eight flip-flops, only some slices can use their LUTs as distributed RAM or SRLs.
2.
Each DSP48E1 slice contains a 25 x 18 multiplier, an adder, and an accumulator.
3.
Block RAMs are fundamentally 36 Kbits in size. Each block can also be used as two independent 18 Kb blocks.
4.
Each CMT contains two mixed-mode clock managers (MMCM).
5.
This table lists individual Ethernet MACs per device.
6.
Does not include configuration Bank 0.
7.
This number does not include GTX or GTH transceivers.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC6VHX380T | 制造商:IXYS 制造商全稱:IXYS Corporation 功能描述:Virtex-6 Family Overview |
| XC6VHX380T-1FF1154C | 制造商:Xilinx 功能描述:VIRTEX6HXT - Trays 制造商:Xilinx 功能描述:IC FPGA 320 I/O 1156FCBGA |
| XC6VHX380T-1FF1154I | 制造商:Xilinx 功能描述:VIRTEX6HXT - Trays 制造商:Xilinx 功能描述:IC FPGA 320 I/O 1156FCBGA 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 380K 1154BGA |
| XC6VHX380T-1FF1155C | 制造商:Xilinx 功能描述:VIRTEX6HXT - Trays 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 380K 1155BGA |
| XC6VHX380T-1FF1155I | 制造商:Xilinx 功能描述:IC FPGA 440 I/O 1156FCBGA |
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