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參數(shù)資料
| 型號： | XC6VLX550T-L1FFG1759C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA VIRTEX 6 549K 1759FFGBGA |
| 產(chǎn)品培訓模塊： | Virtex-6 FPGA Overview |
| 產(chǎn)品變化通告： | Virtex-6 FIFO Input Logic Reset 18/Apr/2011 |
| 標準包裝： | 1 |
| 系列： | Virtex® 6 LXT |
| LAB/CLB數(shù)： | 42960 |
| 邏輯元件/單元數(shù)： | 549888 |
| RAM 位總計： | 23298048 |
| 輸入/輸出數(shù)： | 840 |
| 電源電壓： | 0.87 V ~ 0.93 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 1759-BBGA，F(xiàn)CBGA |
| 供應商設備封裝： | 1759-FCBGA |
Virtex-6 Family Overview
DS150 (v2.4) January 19, 2012
Product Specification
5
Clock Management
Each Virtex-6 FPGA has up to nine clock management tiles (CMTs), each consisting of two mixed-mode clock managers
(MMCMs), which are PLL based.
Phase-Locked Loop
The MMCM can serve as a frequency synthesizer for a wider range of frequencies and as a jitter filter for incoming clocks.
The heart of the MMCM is a voltage-controlled oscillator (VCO) with a frequency from 600 MHz up to 1600 MHz, spanning
more than one octave. There are three sets of programmable frequency dividers (D, M, and O).
The pre-divider D (programmable by configuration) reduces the input frequency and feeds one input of the traditional PLL
phase/frequency comparator. The feedback divider (programmable by configuration) acts as a multiplier because it divides
the VCO output frequency before feeding the other input of the phase comparator. D and M must be chosen appropriately
to keep the VCO within its specified frequency range.
The VCO has eight equally-spaced output phases (0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). Each can be selected to
drive one of the seven output dividers, O0 to O6 (each programmable by configuration to divide by any integer from 1 to 128).
MMCM Programmable Features
The MMCM has three input-jitter filter options: low bandwidth, high bandwidth, or optimized mode. Low-bandwidth mode has
the best jitter attenuation but not the smallest phase offset. High-bandwidth mode has the best phase offset, but not the best
jitter attenuation. Optimized mode allows the tools to find the best setting.
The MMCM can have a fractional counter in either the feedback path (acting as a multiplier) or in one output path. Fractional
counters allow non-integer increments of 1/8 and can thus increase frequency synthesis capabilities by a factor of 8.
The MMCM can also provide fixed or dynamic phase shift in small increments that depend on the VCO frequency. At
600 MHz the phase-shift timing increment is 30 ps; at 1600 MHz, it is 11.5 ps.
Clock Distribution
Each Virtex-6 FPGA provides five different types of clock lines (BUFG, BUFR, BUFIO, BUFH, and the high-performance
clock) to address the different clocking requirements of high fanout, short propagation delay, and extremely low skew.
Global Clock Lines
In each Virtex-6 FPGA, 32 global-clock lines have the highest fanout and can reach every flip-flop clock, clock enable,
set/reset, as well as many logic inputs. There are 12 global clock lines within any region. Global clock lines can be driven by
global clock buffers, which can also perform glitchless clock multiplexing and the clock enable function. Global clocks are
often driven from the CMT, which can completely eliminate the basic clock distribution delay.
Regional Clocks
Regional clocks can drive all clock destinations in their region as well as the region above and below. A region is defined as
any area that is 40 I/O and 40 CLB high and half the chip wide. Virtex-6 FPGAs have between 6 and 18 regions. There are
6 regional clock tracks in every region. Each regional clock buffer can be driven from either of four clock-capable input pins,
and its frequency can optionally be divided by any integer from 1 to 8.
I/O Clocks
I/O clocks are especially fast and serve only I/O logic and serializer/deserializer (SerDes) circuits, as described in the I/O
Logic section. Virtex-6 devices have a high-performance direct connection from the MMCM to the I/O directly for low-jitter,
high-performance interfaces.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| XC6VLX550T-L1FFG1759I | 功能描述:IC FPGA VIRTEX 6 549K 1759FFGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 6 LXT 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55） |
| XC6VLX550T-L1FFG1760C | 功能描述:IC FPGA VIRTEX 6 549K 1760FFGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 6 LXT 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55） |
| XC6VLX550T-L1FFG1760I | 功能描述:IC FPGA VIRTEX 6 549K 1760FFGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 6 LXT 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55） |
| XC6VLX75_11 | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-6 Family Overview |
| XC6VLX75T | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-6 FPGA Data Sheet: DC and Switching Characteristics |
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