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參數(shù)資料
| 型號： | XC6VLX760-L1FFG1760I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA VIRTEX 6 758K 1760FFGBGA |
| 產(chǎn)品培訓(xùn)模塊： | Virtex-6 FPGA Overview |
| 產(chǎn)品變化通告： | Virtex-6 FIFO Input Logic Reset 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex® 6 LXT |
| LAB/CLB數(shù)： | 59280 |
| 邏輯元件/單元數(shù)： | 758784 |
| RAM 位總計： | 26542080 |
| 輸入/輸出數(shù)： | 1200 |
| 電源電壓： | 0.91 V ~ 0.97 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 1760-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 1760-FCBGA |
Virtex-6 Family Overview
DS150 (v2.4) January 19, 2012
Product Specification
4
Configuration
Virtex-6 FPGAs store their customized configuration in SRAM-type internal latches. The number of configuration bits is
between 26 Mb and 177 Mb, depending on device size but independent of the specific user-design implementation, unless
compression mode is used. The configuration storage is volatile and must be reloaded whenever the FPGA is powered up.
This storage can also be reloaded at any time by pulling the PROGRAM_B pin Low. Several methods and data formats for
loading configuration are available, determined by the three mode pins.
Bit-serial configurations can be either master serial mode where the FPGA generates the configuration clock (CCLK) signal,
or slave serial mode where the external configuration data source also clocks the FPGA. For byte- and word-wide
configurations, master SelectMAP mode generates the CCLK signal while slave SelectMAP mode receives the CCLK signal
for the 8-, 16-, or 32-bit-wide transfer. Alternatively, serial-peripheral interface (SPI) and byte-peripheral interface (BPI)
modes are used with industry-standard flash memories and are clocked by the CCLK output of the FPGA. JTAG mode uses
boundary-scan protocols to load bit-serial configuration data.
The bitstream configuration information is generated by the ISE software using a program called BitGen. The configuration
process typically executes the following sequence:
Detects power-up (power-on reset) or PROGRAM_B when Low.
Clears the whole configuration memory.
Samples the mode pins to determine the configuration mode: master or slave, bit-serial or parallel, or bus width.
Loads the configuration data starting with the bus-width detection pattern followed by a synchronization word, checks
for the proper device code, and ends with a cyclic redundancy check (CRC) of the complete bitstream.
Start-up executes a user-defined sequence of events: releasing the internal reset (or preset) of flip-flops, optionally
waiting for the phase-locked loops (PLLs) to lock and/or the DCI to match, activating the output drivers, and transitions
the DONE pin High.
Dynamic Reconfiguration Port
The dynamic reconfiguration port (DRP) gives the system designer easy access to configuration bits and status registers for
three block types: 32 locations for each clock tile, 128 locations for the System Monitor, and 128 locations for each serial
GTX or GTH transceiver.
The DRP behaves like memory-mapped registers, and can access and modify block-specific configuration bits as well as
status and control registers.
Encryption, Readback, and Partial Reconfiguration
As a special option, the bitstream can be AES-encrypted to prevent unauthorized copying of the design. The Virtex-6 FPGA
performs the decryption using the internally stored 256-bit key that can use battery backup or alternative non-volatile
storage.
Most configuration data can be read back without affecting the system’s operation. Typically, configuration is an all-or-
nothing operation, but the Virtex-6 FPGA also supports partial reconfiguration. When applicable in certain designs, partial
reconfiguration can greatly improve the versatility of the FPGA. It is even possible to reconfigure a portion of the FPGA while
the rest of the logic remains active i.e., active partial reconfiguration.
CLBs, Slices, and LUTs
The look-up tables (LUTs) in Virtex-6 FPGAs can be configured as either one 6-input LUT (64-bit ROMs) with one output, or
as two 5-input LUTs (32-bit ROMs) with separate outputs but common addresses or logic inputs. Each LUT output can
optionally be registered in a flip-flop. Four such LUTs and their eight flip-flops as well as multiplexers and arithmetic carry
logic form a slice, and two slices form a configurable logic block (CLB). Four flip-flops per slice (one per LUT) can optionally
be configured as latches. In that case, the remaining four flip-flops in that slice must remain unused.
Between 25–50% of all slices can also use their LUTs as distributed 64-bit RAM or as 32-bit shift registers (SRL32) or as two
SRL16s. Modern synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features. Expert
designers can also instantiate them.
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| XC6VSX315T-1FF1156I | 功能描述:IC FPGA VIRTEX-6SXT 1156FFBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 6 SXT 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
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