參數(shù)資料
型號: XC7K420T-1LFFG1156C
廠商: XILINX INC
元件分類: FPGA
英文描述: FPGA, PBGA1156
封裝: LEAD FREE, FBGA-1156
文件頁數(shù): 26/50頁
文件大小: 1218K
代理商: XC7K420T-1LFFG1156C
Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics
DS182 (v1.1) April 1, 2011
Advance Product Specification
32
CLB Distributed RAM Switching Characteristics (SLICEM Only)
Set/Reset
TSRMIN
SR input minimum pulse width
0.50
0.75
1.00
ns, Min
TRQ
Delay from SR input to AQ – DQ flip-flops
0.55
0.61
0.71
ns, Max
TCEO
Delay from CE input to AQ – DQ flip-flops
0.44
0.51
0.61
ns, Max
FTOG
Toggle frequency (for export control)
1412
1286
1098
MHz
Notes:
1.
A Zero “0” Hold Time listing indicates no hold ti
me or a negative hold time. Negative values can not be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
2.
These items are of interest for Carry Chain applications.
Table 36: CLB Distributed RAM Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
-1L
Sequential Delays
TSHCKO
Clock to A – B outputs
0.99
1.18
1.46
ns, Max
TSHCKO_1
Clock to AMUX – BMUX outputs
1.26
1.48
1.80
ns, Max
Setup and Hold Times Before/After Clock CLK
TDS_LRAM/TDH_LRAM
A – D inputs to CLK
0.64/
0.21
0.75/
0.23
0.91/
0.26
ns, Min
TAS_LRAM/TAH_LRAM
Address An inputs to clock
0.17/
0.46
0.21/
0.50
0.26/
0.58
ns, Min
TWS_LRAM/TWH_LRAM WE input to clock
0.27/
0.03
0.33/
0.03
0.41/
0.03
ns, Min
TCECK_LRAM/
TCKCE_LRAM
CE input to CLK
0.28/
0.02
0.34/
0.02
0.42/
0.02
ns, Min
Clock CLK
TMPW_LRAM
Minimum pulse width
0.77
0.90
1.09
ns, Min
TMCP
Minimum clock period
1.53
1.79
2.18
ns, Min
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
2.
TSHCKO also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path.
Table 35: CLB Switching Characteristics (Cont’d)
Symbol
Description
Speed Grade
Units
-3
-2
-1
-1L
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