參數(shù)資料
型號: XC7K420T-3FFG1156E
廠商: XILINX INC
元件分類: FPGA
英文描述: FPGA, PBGA1156
封裝: LEAD FREE, FBGA-1156
文件頁數(shù): 39/50頁
文件大?。?/td> 1218K
代理商: XC7K420T-3FFG1156E
Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics
DS182 (v1.1) April 1, 2011
Advance Product Specification
44
PLL Switching Characteristics Setup and Hold
TPLLCCK_DEN/
TPLLCKC_DEN
Setup and Hold of D enable
1.76/
0.00
1.97/
0.00
2.29/
0.00
ns
TPLLCCK_DADDR/
TPLLCKC_DADDR
Setup and Hold of D address
1.25/
0.00
1.40/
0.00
1.63/
0.00
ns
TPLLCCK_DI/
TPLLCKC_DI
Setup and Hold of D input
1.25/
0.00
1.40/
0.00
1.63/
0.00
ns
TPLLCCK_DWE/
TPLLCKC_DWE
Setup and Hold of D write enable
1.25/
0.00
1.40/
0.00
1.63/
0.00
ns
Notes:
1.
The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2.
The static offset is measured between any PLL outputs with identical phase.
3.
Values for this parameter are available in the Architecture Wizard.
4.
Includes global clock buffer.
5.
Calculated as FVCO/128 assuming output duty cycle is 50%.
6.
When CASCADE4_OUT = TRUE, FOUTMIN is 0.036 MHz.
Table 46: PLL Specification (Cont’d)
Symbol
Description
Speed Grade
Units
-3
-2
-1
-1L
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