參數(shù)資料
型號(hào)： XC7K420T-3FFG901I
廠商： XILINX INC
元件分類： FPGA
英文描述： FPGA, PBGA900
封裝： LEAD FREE, FBGA-900
文件頁數(shù)： 45/50頁
文件大小： 1218K
代理商： XC7K420T-3FFG901I
Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics
DS182 (v1.1) April 1, 2011
Advance Product Specification
5
SelectIO DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended
operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that
all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and
VOH voltage levels shown. Other standards are sample tested.
Table 7: SelectIO DC Input and Output Levels (1)(2)
I/O Standard
VIL
VIH
VOL
VOH
IOL
IOH
V, Min
V, Max
V, Min
V, Max
V, Min
mA
LVTTL
–0.3
0.8
2.0
3.45
0.4
2.4
Note 3
LVCMOS33
–0.3
0.8
2.0
3.45
0.4
VCCO – 0.4
Note 4
LVCMOS25
–0.3
0.7
1.7
VCCO +0.3
0.4
VCCO – 0.4
Note 4
LVCMOS18,
LVDCI18
–0.3
35% VCCO
65% VCCO
VCCO + 0.3
0.45
VCCO – 0.45
Note 5
LVCMOS15,
LVDCI15
–0.3
30% VCCO
70% VCCO
VCCO + 0.3
25% VCCO
75% VCCO
Note 6
LVCMOS12
–0.3
35% VCCO
65% VCCO
VCCO + 0.3
25% VCCO
75% VCCO
Note 7
PCI33_3
–0.5
30% VCCO
50% VCCO
VCCO + 0.5
10% VCCO
90% VCCO
1.5
–0.5
HSTL I_12
–0.3
VREF –0.1
VREF +0.1
VCCO + 0.3
25% VCCO
75% VCCO
6.3
HSTL I(8)
–0.3
VREF –0.1
VREF +0.1
VCCO +0.3
0.4
VCCO –0.4
8
–8
HSTL II(8)
–0.3
VREF –0.1
VREF +0.1
VCCO +0.3
0.4
VCCO –0.4
16
–16
DIFF HSTL I(8)
–0.3
50% VCCO – 0.1 50% VCCO +0.1
VCCO +0.3
–
DIFF HSTL II(8)
–0.3
50% VCCO – 0.1 50% VCCO +0.1
VCCO +0.3
–
SSTL135
–0.3
VREF –0.15
VREF +0.15
VCCO +0.3
DIFF SSTL135
–0.3
50%
VCCO –0.15
50%
VCCO +0.15
VCCO +0.3
SSTL18 I
–0.3
VREF – 0.125
VREF + 0.125
VCCO +0.3
VTT –0.47
VTT +0.47
8
–8
SSTL18 II
–0.3
VREF – 0.125
VREF +0.125
VCCO +0.3
VTT –0.60
VTT + 0.60
13.4
–13.4
DIFF SSTL18 I
–0.3
50%
VCCO –0.125
50%
VCCO +0.125
VCCO +0.3
VTT –0.608
VTT + 0.608
–
DIFF SSTL18 II
–0.3
50%
VCCO –0.125
50%
VCCO +0.125
VCCO +0.3
–
SSTL15
–0.3
VREF –0.1
VREF +0.1
VCCO +0.3
VTT –0.175
VTT + 0.175
17.8
Notes:
1.
Tested according to relevant specifications.
2.
3.3V and 2.5V standards are only supported in 3.3V I/O banks.
3.
Supported drive strengths of 4, 8, 12, 16, or 24 mA
4.
Supported drive strengths of 4, 8, 12, or 16 mA
5.
Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, 16, or 24 mA in HR I/O banks.
6.
Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, or 16 mA in HR I/O banks.
7.
Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks and 4, 8, or 12 mA in HR I/O banks.
8.
Applies to both 1.5V and 1.8V HSTL.
9.
For detailed interface specific DC voltage levels, see UG471: 7 Series FPGAs SelectIO Resources User Guide.
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