參數(shù)資料
型號(hào): XC95144XL-10TQ100I
廠商: Xilinx Inc
文件頁(yè)數(shù): 9/12頁(yè)
文件大小: 0K
描述: IC CPLD 144MCELL 10NS 100TQFP
標(biāo)準(zhǔn)包裝: 90
系列: XC9500XL
可編程類(lèi)型: 系統(tǒng)內(nèi)可編程(最少 10,000 次編程/擦除循環(huán))
最大延遲時(shí)間 tpd(1): 10.0ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目: 8
宏單元數(shù): 144
門(mén)數(shù): 3200
輸入/輸出數(shù): 81
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤(pán)
XC95144XL High Performance CPLD
6
DS056 (v2.0) April 3, 2007
Product Specification
R
Internal Timing Parameters
Symbol
Parameter
XC95144XL-5
XC95144XL-7
XC95144XL-10
Units
Min
Max
Min
Max
Min
Max
Buffer Delays
TIN
Input buffer delay
-
1.5
-
2.3
-
3.5
ns
TGCK
GCK buffer delay
-
1.1
-
1.5
-
1.8
ns
TGSR
GSR buffer delay
-
2.0
-
3.1
-
4.5
ns
TGTS
GTS buffer delay
-
4.0
-
5.0
-
7.0
ns
TOUT
Output buffer delay
-
2.0
-
2.5
-
3.0
ns
TEN
Output buffer enable/disable
delay
-0
-
0
ns
Product Term Control Delays
TPTCK
Product term clock delay
-
1.6
-
2.4
-
2.7
ns
TPTSR
Product term set/reset delay
-
1.0
-
1.4
-
1.8
ns
TPTTS
Product term 3-state delay
-
5.5
-
7.2
-
7.5
ns
Internal Register and Combinatorial Delays
TPDI
Combinatorial logic propagation delay
-
0.5
-
1.3
-
1.7
ns
TSUI
Register setup time
2.3
-
2.6
-
3.0
-
ns
THI
Register hold time
1.4
-
2.2
-
3.5
-
ns
TECSU
Register clock enable setup time
2.3
-
2.6
-
3.0
-
ns
TECHO
Register clock enable hold time
1.4
-
2.2
-
3.5
-
ns
TCOI
Register clock to output valid time
-
0.4
-
0.5
-
1.0
ns
TAOI
Register async. S/R to output delay
-
6.0
-
6.4
-
7.0
ns
TRAI
Register async. S/R recover before clock
5.0
7.5
10.0
ns
TLOGI
Internal logic delay
-
1.0
-
1.4
-
1.8
ns
TLOGILP Internal low power logic delay
-
5.0
-
6.4
-
7.3
ns
Feedback Delays
TF
Fast CONNECT II feedback delay
-
1.9
-
3.5
-
4.2
ns
Time Adders
TPTA
Incremental product term allocator delay
-
0.7
-
0.8
-
1.0
ns
TSLEW
Slew-rate limited delay
-
3.0
-
4.0
-
4.5
ns
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