參數(shù)資料
型號(hào): XC9572XV-7VQ44C
廠商: Xilinx Inc
文件頁(yè)數(shù): 5/9頁(yè)
文件大?。?/td> 0K
描述: IC CPLD 2.5V ISP 44-VQFP
產(chǎn)品變化通告: Product Discontinuation Notice 14/May/2007
標(biāo)準(zhǔn)包裝: 160
系列: XC9500XV
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 7.5ns
電壓電源 - 內(nèi)部: 2.37 V ~ 2.62 V
邏輯元件/邏輯塊數(shù)目: 4
宏單元數(shù): 72
門數(shù): 1600
輸入/輸出數(shù): 34
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 44-TQFP
供應(yīng)商設(shè)備封裝: 44-VQFP(10x10)
包裝: 托盤
XC9572XV High-performance CPLD
DS052 (v3.0) June 25, 2007
5
Product Specification
R
Internal Timing Parameters
Figure 3: AC Load Circuit
Symbol
Parameter
XC9572XV-5
XC9572XV-7
Units
Min
Max
Min
Max
Buffer Delays
TIN
Input buffer delay
-
2.0
-
2.3
ns
TGCK
GCK buffer delay
-
1.2
-
1.5
ns
TGSR
GSR buffer delay
-
2.0
-
3.1
ns
TGTS
GTS buffer delay
-
4.0
-
5.0
ns
TOUT
Output buffer delay
-
2.1
-
2.5
ns
TEN
Output buffer enable/disable delay
-
0
-
0
ns
Product Term Control Delays
TPTCK
Product term clock delay
-
1.7
-
2.4
ns
TPTSR
Product term set/reset delay
-
0.7
-
1.4
ns
TPTTS
Product term 3-state delay
-
5.0
-
7.2
ns
Internal Register and Combinatorial Delays
TPDI
Combinatorial logic propagation delay
-
0.2
-
1.3
ns
TSUI
Register setup time
2.0
-
2.6
-
ns
THI
Register hold time
1.5
-
2.2
-
ns
TECSU
Register clock enable setup time
2.0
-
2.6
-
ns
TECHO
Register clock enable hold time
1.5
-
2.2
-
ns
TCOI
Register clock to output valid time
-
0.2
-
0.5
ns
TAOI
Register async. S/R to output delay
-
5.9
-
6.4
ns
TRAI
Register async. S/R recover before clock
5.0
7.5
ns
TLOGI
Internal logic delay
-
0.7
-
1.4
ns
TLOGILP
Internal low power logic delay
-
5.7
-
6.4
ns
Feedback Delays
TF
Fast CONNECT II feedback delay
-
1.6
-
3.5
ns
Time Adders
TPTA
Incremental product term allocator delay
-
0.7
-
0.8
ns
TPTA2
Adjacent macrocell p-term allocator delay
-
0.3
-
0.3
ns
TSLEW
Slew-rate limited delay
-
3.0
-
4.0
ns
R1
VTEST
CL
R2
Device Output
Output Type
VTEST
3.3V
2.5V
1.8V
R1
320
Ω
250
Ω
10K
Ω
R2
360
Ω
660
Ω
14K
Ω
CL
35 pF
DS051_03_0601000
VCCIO
3.3V
2.5V
1.8V
Product Obsolete/Under Obsolescence
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