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參數(shù)資料
| 型號： | XCR3032XL-10CS48I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 3.3V ZERO PWR 48-CSP |
| 標(biāo)準(zhǔn)包裝： | 416 |
| 系列： | CoolRunner XPLA3 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 1K 次編程/擦除循環(huán)） |
| 最大延遲時(shí)間 tpd(1)： | 9.1ns |
| 電壓電源 - 內(nèi)部： | 2.7 V ~ 3.6 V |
| 邏輯元件/邏輯塊數(shù)目： | 2 |
| 宏單元數(shù)： | 32 |
| 門數(shù)： | 750 |
| 輸入/輸出數(shù)： | 36 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-FBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 48-CSBGA（7x7） |
| 包裝： | 托盤 |
CoolRunner XPLA3 CPLD
10
DS012 (v2.5) May 26, 2009
Product Specification
R
Absolute Maximum Ratings
Table 7: Programming Specifications
Symbol
Parameter
Min.
Max.
Unit
DC Parameters
VCCP
VCC supply program/verify
3.0
3.6
V
ICCP
ICC limit program/verify(1)
-30
mA
VIH
Input voltage (High)
2.0
-
V
VIL
Input voltage (Low)
-
0.8
V
VOL
Output voltage (Low)
-
0.4
V
VOH
Output voltage (High)
2.4
-
V
AC Parameters
FMAX
TCK maximum frequency
-
10
MHz
PWE
Pulse width erase
100
-
ms
PWP
Pulse width program
10
-
ms
PWV
Pulse width verify
10
-
μs
TINIT
Initialization time(1)
-200
μs
TMS_SU
TMS setup time before TCK
↑
10
-
ns
TDI_SU
TDI setup time before TCK
↑
10
-
ns
TMS_H
TMS hold time after TCK
↑
20
-
ns
TDI_H
TDI hold time after TCK
↑
20
-
ns
TDO_CO
TDO valid after TCK
↓
-30
ns
Notes:
1.
Family specification. See individual device data sheets for specific device measurements.
Symbol
Parameter(1)
Min.
Max.
Unit
VCC
Supply voltage(2) relative to GND
–0.5
4.0
V
VI
Input voltage(3) relative to GND
–0.5
5.5(4)
V
IOUT
Output current, per pin
–100
100
mA
TJ
Maximum junction temperature
–40
150
°C
TSTR
Storage temperature
–65
150
°C
Notes:
1.
Stresses above those listed might cause malfunction or permanent damage to the device. This is a stress rating only. Functional
operation at these or any other condition above those indicated in the operational and programming specification is not implied.
2.
The chip supply voltage must rise monotonically.
3.
Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins can undershoot to –2.0V or overshoot to 7.0V, provided this over- or undershoot lasts less than 10 ns and with the forcing
current being limited to 200 mA.
4.
External I/O voltage must not exceed VCC by 4.0V.
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| XCR3032XL-10CSG48C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 750 GATES 32 MCRCLLS 125MHZ 0.35UM 3.3 - Trays 制造商:Xilinx 功能描述:XLXXCR3032XL-10CSG48C IC SYSTEM GATE |
| XCR3032XL-10CSG48I | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 750 GATES 32 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
| XCR3032XL-10PC44C | 制造商:XILINX 制造商全稱:XILINX 功能描述:XCR3032XL 32 Macrocell CPLD |
| XCR3032XL-10PC44I | 功能描述:IC CPLD 3.3V ZERO PWR 44-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner XPLA3 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| XCR3032XL-10VQ44C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 750 GATES 32 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
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