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參數(shù)資料
| 型號(hào)： | XCR3064XL-10VQG100C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CR CPLD 1.5K 64MCELL 100-VQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | CoolRunner XPLA3 |
| 可編程類(lèi)型： | 系統(tǒng)內(nèi)可編程（最少 1K 次編程/擦除循環(huán)） |
| 最大延遲時(shí)間 tpd(1)： | 9.1ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 邏輯元件/邏輯塊數(shù)目： | 4 |
| 宏單元數(shù)： | 64 |
| 門(mén)數(shù)： | 1500 |
| 輸入/輸出數(shù)： | 68 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-VQFP（14x14） |
| 包裝： | 托盤(pán) |
| 產(chǎn)品目錄頁(yè)面： | 600 (CN2011-ZH PDF) |
| 其它名稱(chēng)： | 122-1470 |
CoolRunner XPLA3 CPLD
DS012 (v2.5) May 26, 2009
Product Specification
R
JTAG Testing Capability
JTAG is the commonly used acronym for the Boundary
Scan Test (BST) feature defined for integrated circuits by
IEEE Standard 1149.1. This standard defines input/output
pins, logic control functions, and commands that facilitate
both board and device level testing without the use of spe-
cialized test equipment. CoolRunner XPLA3 devices use
the JTAG Interface for In-System Programming/Reprogram-
ming. The JTAG command set is implemented as described
in Table 4.
As implemented in CoolRunner XPLA3 CPLDs, the JTAG
Port includes four of the five pins (refer to Table 5) described
in the JTAG specification: TCK, TMS, TDI, and TDO. The
fifth signal defined by the JTAG specification is TRST (Test
Reset). TRST is considered an optional signal, since it is
not actually required to perform BST or ISP. The CoolRun-
ner XPLA3 CPLD saves an I/O pin for general purpose use
by not implementing the optional TRST signal in the JTAG
interface. Instead, the CoolRunner XPLA3 CPLD supports
the test reset functionality through the use of its power-up
reset circuit.
Port Enable Pin
The Port Enable pin is used to reclaim TMS, TDO, TDI, and
TCK for JTAG ISP programming if the user has defined
these pins as general purpose I/O during device program-
ming. For ease of use, CoolRunner XPLA3 devices are
shipped with the JTAG port pins enabled. The Port Enable
pin must be a low logic level during the power-up sequence
for the device to operate properly.
During device programming, the JTAG ISP pins can be left
as is or reconfigured as user specific I/O pins. If the JTAG
ISP pins have been used for I/O pins, simply applying a high
logic level to the Port Enable pin converts the JTAG ISP pins
back to their respective programming function and the
device can be reprogrammed via ISP. After completing the
desired JTAG ISP programming function, simply return Port
Enable to Ground to re-establish the JTAG ISP pins to their
respective I/O function. Reconfiguring the JTAG port pins as
I/Os makes these pins non-JTAG ISP functional until
reclaimed by port enable.
If the JTAG pins are not required as I/O, port enable should
be permanently tied to GND. Pins associated with the JTAG
port have internal weak pull ups enabled to terminate the
pins. However, in noisy environments, external 10K pull ups
are recommended.
The CoolRunner XPLA3 family allows the macrocells asso-
ciated with these pins to be used as buried logic when the
JTAG/ISP function is enabled.
Figure 8: XPLA3 Timing Model
TIN
TF
TOUT
TEN
TSLEW
TLOGI1,2
TPTCK
DLT
Q
CE
S/R
TLOGI3
TFIN
TGCK
TUDA
DS017_02_031802
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