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參數(shù)資料
| 型號(hào)： | XCR3064XL-10VQG44I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 1.5K 64MCELL HP 44-VQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | CoolRunner XPLA3 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 1K 次編程/擦除循環(huán)） |
| 最大延遲時(shí)間 tpd(1)： | 9.1ns |
| 電壓電源 - 內(nèi)部： | 2.7 V ~ 3.6 V |
| 邏輯元件/邏輯塊數(shù)目： | 4 |
| 宏單元數(shù)： | 64 |
| 門數(shù)： | 1500 |
| 輸入/輸出數(shù)： | 36 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-TQFP |
| 供應(yīng)商設(shè)備封裝： | 44-VQFP（10x10） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 600 (CN2011-ZH PDF) |
| 其它名稱： | 122-1469 |
CoolRunner XPLA3 CPLD
6
DS012 (v2.5) May 26, 2009
Product Specification
R
Power-Up Characteristics
During power-up, the CoolRunner XPLA3 device I/Os may
be undefined until VCC rises above 1.0V. This time period is
called the Subthreshold State, as transistors have not yet
fully been turned on. When VCC rises above 1.0V, the
device I/Os enter the Quiescent State, and I/Os are dis-
abled with weak pull-ups as shown in Table 3. When VCC
reaches the threshold of the User Operation State (approx-
imately 2.1V), user registers are initialized (typically within
200
μs) after which I/Os assume the behavior determined
by the user pattern, as shown in Figure 7.
If the device is in the erased state (before any user pattern
is programmed), the device outputs remain disabled with
weak pull-ups. The JTAG pins are enabled to allow the
device to be programmed at any time. All devices are
shipped in the erased state from the factory.
If the device is programmed, the device inputs and outputs
take on their configured states for normal operation.
Security
Designs can be secured during programming to prevent
pattern theft via readback. This security setting does not
protect readback of the Usercode/signature space, which is
often used for storing application serial numbers or revision
codes. The only way to clear the security setting is to com-
pletely erase the entire device.
Timing Model
The CoolRunner XPLA3 architecture follows a timing model
that allows deterministic timing in design and redesign. The
basic timing model is shown in Figure 8. There is a fast path
(TLOGI1) into the macrocell which is used if there is a single
product term. The TLOGI2 path is used for multiple product
term timing. For optimization of logic, the CoolRunner
XPLA3 CPLD architecture includes a Foldback NAND path
(TLOGI3). There is a fast input path to each macrocell if used
as an Input Register (TFIN). The CoolRunner XPLA3 archi-
tecture also includes universal control terms (TUDA) that can
be used for synchronization of the macrocell registers in dif-
ferent function blocks. There is slew rate control and output
enable control on a per macrocell basis.
Figure 7: Device Behavior During Power Up
V CC
No
Power
3.8 V
(Typ)
0V
No
Power
Quiescent
State
Quiescent
State
User Operation State
Initialization of User Registers
DS012_12_082707
2.1V
1.6V
(Typ)
Subthreshold
State
1.0V
Table 3: I/O Power-Up Characteristics
Device Circuitry
Subthreshold State
Quiescent State
Erased Device Operation Valid User Operation
Device I/Os
Undetermined
Disabled with Weak
Pull-up
Disabled with Weak
Pull-up
As Configured
Device
Inputs/Clocks
Undetermined
High-Z
JTAG Controller
Undetermined
Disabled with Weak
Pull-up
Enabled
As Configured
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