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參數(shù)資料
| 型號： | XCS05-3CS208C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Silver Mica Capacitor; Capacitance:100pF; Capacitance Tolerance:+/- 2%; Series:CD5; Voltage Rating:300VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:3mm; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| 中文描述： | 斯巴達和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 19/66頁 |
| 文件大?。?/td> | 809K |
| 代理商： | XCS05-3CS208C |
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R
DS060 (v1.5) March 2, 2000
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4-19
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Figure 20
is a diagram of the Spartan/XL boundary scan
logic. It includes three bits of Data Register per IOB, the
IEEE 1149.1 Test Access Port controller, and the Instruc-
tion Register with decodes.
Spartan/XL devices can also be configured through the
boundary scan logic. See
“
Configuration Through the
Boundary Scan Pins
”
on page 31
.
Data Registers
The primary data register is the boundary scan register. For
each IOB pin in the FPGA, bonded or not, it includes three
bits for In, Out and 3-state Control. Non-IOB pins have
appropriate partial bit population for In or Out only. PRO-
GRAM, CCLK and DONE are not included in the boundary
scan register. Each EXTEST CAPTURE-DR state captures
all In, Out, and 3-state pins.
The data register also includes the following non-pin bits:
TDO.T, and TDO.O, which are always bits 0 and 1 of the
data register, respectively, and BSCANT.UPD, which is
always the last bit of the data register. These three bound-
ary scan bits are special-purpose Xilinx test signals.
The other standard data register is the single flip-flop
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream boundary scan
device.
The FPGA provides two additional data registers that can
be specified using the BSCAN macro. The FPGA provides
two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are
the decodes of two user instructions. For these instructions,
two
corresponding
pins
BSCAN.TDO2) allow user scan data to be shifted out on
TDO. The data register clock (BSCAN.DRCK) is available
for control of test logic which the user may wish to imple-
ment with CLBs. The NAND of TCK and RUN-TEST-IDLE
is also provided (BSCAN.IDLE).
(BSCAN.TDO1
and
Instruction Set
The Spartan/XL boundary scan instruction set also
includes instructions to configure the device and read back
the configuration data. The instruction set is coded as
shown in
Table 12
.
D
Q
D
Q
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
M
U
X
BYPASS
REGISTER
IOB
IOB
TDO
TDI
IOB
IOB
IOB
1
0
1
0
1
0
1
0
1
0
sd
LE
D
Q
D
Q
D
Q
1
0
1
0
1
0
1
0
D
Q
LE
sd
sd
LE
D
Q
sd
LE
D
Q
IOB
D
Q
1
0
D
Q
LE
sd
IOB.T
DATA IN
IOB.I
IOB.Q
IOB.T
IOB.I
SHIFT/
CAPTURE
CLOCK DATA
REGISTER
DATAOUT
UPDATE
EXTEST
X9016
INSTRUCTION REGISTER
Figure 20: Spartan/XL Boundary Scan Logic
相關PDF資料 |
PDF描述 |
|---|---|
| XCS05-3CS208I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3CS240C | Silver Mica Capacitor; Capacitance:100pF; Capacitance Tolerance:+/- 5%; Series:CD5; Voltage Rating:300VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:3mm; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| XCS05-3CS240I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3CS256C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3CS256I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XCS05-3CS208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3CS240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3CS240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3CS256C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3CS256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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