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參數(shù)資料
| 型號： | XCS05-3PC256I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 22/66頁 |
| 文件大?。?/td> | 809K |
| 代理商： | XCS05-3PC256I |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
4-22
DS060 (v1.5) March 2, 2000
Note that the PWRDWN pin is not part of the Boundary
Scan chain. Therefore, the Spartan-XL family has a sepa-
rate set of BSDL files than the 5V Spartan family. Boundary
scan logic is not usable during Power Down.
Configuration and Test
Configuration is the process of loading design-specific pro-
gramming data into one or more FPGAs to define the func-
tional operation of the internal blocks and their
interconnections. This is somewhat like loading the com-
mand registers of a programmable peripheral chip. Spar-
tan/XL devices use several hundred bits of configuration
data per CLB and its associated interconnects. Each con-
figuration bit defines the state of a static memory cell that
controls either a function look-up table bit, a multiplexer
input, or an interconnect pass transistor. The Xilinx devel-
opment system translates the design into a netlist file. It
automatically partitions, places and routes the logic and
generates the configuration data in PROM format.
Configuration Mode Control
5V Spartan devices have two configuration modes.
MODE = 1 sets Slave Serial mode
MODE = 0 sets Master Serial mode
3V Spartan-XL devices have three configuration modes.
M1/M0 = 11 sets Slave Serial mode
M1/M0 = 10 sets Master Serial mode
M1/M0 = 0X sets Express mode
In addition to these modes, the device can be configured
through the Boundary Scan logic (
See
“
Configuration
Through the Boundary Scan Pins
”
on page 31.
).
The Mode pins are sampled prior to starting configuration
to determine the configuration mode. After configuration,
these pin are unused. The Mode pins have a weak pull-up
resistor of 20 k
to 100 k
turned on during configuration.
With the Mode pins High, Slave Serial mode is selected,
which is the most popular configuration mode. Therefore,
for the most common configuration mode, the Mode pins
can be left unconnected. If the Master Serial mode is
desired, the MODE/M0 pin should be connected directly to
GND, or through a pull-down resistor of 1 K
or less.
During configuration, some of the I/O pins are used tempo-
rarily for the configuration process. All pins used during
configuration are shown in
Table 14
and
Table 15
.
Table 14: Pin Functions During Configuration (Spartan
family only)
CONFIGURATION MODE
<MODE Pin>
SLAVE
SERIAL
<High>
MODE (I)
HDC (HIGH)
LDC (LOW)
INIT
DONE
PROGRAM (I)
CCLK (I)
DIN (I)
DOUT
TDI
TCK
TMS
TDO
MASTER
SERIAL
<Low>
MODE (I)
HDC (HIGH)
LDC (LOW)
INIT
DONE
PROGRAM (I)
CCLK (O)
DIN (I)
DOUT
TDI
TCK
TMS
TDO
USER
OPERATION
MODE
I/O
I/O
I/O
DONE
PROGRAM
CCLK (I)
I/O
SGCK4-I/O
TDI-I/O
TCK-I/O
TMS-I/O
TDO-(O)
ALL OTHERS
Notes
1. A shaded table cell represents the internal pull-up
used before and during configuration.
2. (I) represents an input; (O) represents an output.
3. INIT is an open-drain output during configuration.
Table 15: Pin Functions During Configuration
(Spartan-XL family only)
CONFIGURATION MODE <M1:M0>
SLAVE
SERIAL
<1:1>
<1:0>
M1(HIGH) (I)
M1(HIGH) (I)
M0(HIGH) (I)
M0(LOW) (I)
HDC (HIGH)
HDC (HIGH)
LDC (LOW)
LDC (LOW)
INIT
DONE
DONE
PROGRAM (I)
PROGRAM (I)
CCLK (I)
CCLK (O)
MASTER
SERIAL
EXPRESS
<0:X>
M1(LOW) (I)
M0 (I)
HDC (HIGH)
LDC (LOW)
INIT
DONE
PROGRAM (I)
CCLK (I)
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
DOUT
TDI
TCK
TMS
TDO
CS1
USER
OPERATION
M1
M0
I/O
I/O
I/O
INIT
DONE
PROGRAM
CCLK (I)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GCK6-I/O
TDI-I/O
TCK-I/O
TMS-I/O
TDO-(O)
I/O
ALL OTHERS
DIN (I)
DOUT
TDI
TCK
TMS
TDO
DIN (I)
DOUT
TDI
TCK
TMS
TDO
Notes
1. A shaded table cell represents the internal pull-up
used before and during configuration.
2. (I) represents an input; (O) represents an output.
3. INIT is an open-drain output during configuration.
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