• 參數(shù)資料
    型號(hào)： XCS05-4BG256I
    廠商： Xilinx, Inc.
    英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
    中文描述： 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門陣列
    文件頁數(shù)： 49/66頁
    文件大?。?/td> 809K
    代理商： XCS05-4BG256I
    R
    DS060 (v1.5) March 2, 2000
    Powered by ICminer.com Electronic-Library Service CopyRight 2003
    4-49
    Spartan and Spartan-XL Families Field Programmable Gate Arrays
    Spartan-XL CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines (cont.)
    Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
    functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
    representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
    static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
    parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
    Spartan-XL devices and are expressed in nanoseconds unless otherwise noted.
    Spartan-XL CLB RAM Synchronous (Edge-Triggered) Write Timing
    Dual Port RAM
    Speed Grade
    -5
    -4
    Units
    Size
    1
    Symbol
    Min
    Max
    Min
    Max
    Write Operation
    Address write cycle time (clock K period)
    Clock K pulse width (active edge)
    Address setup time before clock K
    DIN setup time before clock K
    WE setup time before clock K
    All hold times after clock K
    Data valid after clock K
    16x1
    16x1
    16x1
    16x1
    16x1
    16x1
    16x1
    T
    WCDS
    T
    WPDS
    T
    ASDS
    T
    DSDS
    T
    WSDS
    T
    WODS
    7.7
    3.1
    1.3
    1.7
    1.4
    0.0
    5.2
    8.4
    3.6
    1.5
    2.0
    1.6
    0.0
    6.1
    ns
    ns
    ns
    ns
    ns
    ns
    ns
    Note 1: Read Operation Timing for 16x1 dual-port RAM option is identical to 16x2 single-port RAM timing.
    WCLK (K)
    WE
    ADDRESS
    DATA IN
    T
    DSDS
    T
    DHDS
    T
    ASDS
    T
    AHDS
    T
    WSDS
    T
    WPDS
    T
    WHDS
    X6474
    DATA OUT
    OLD
    NEW
    T
    WODS
    T
    ILO
    T
    ILO
    X6461
    WCLK (K)
    WE
    ADDRESS
    DATA IN
    DATA OUT
    OLD
    NEW
    T
    DSS
    T
    DHS
    T
    ASS
    T
    AHS
    T
    WSS
    T
    WPS
    T
    WHS
    T
    WOS
    T
    ILO
    T
    ILO
    Single Port
    Dual Port
    相關(guān)PDF資料
    PDF描述
    XCS05-4BG280C Spartan and Spartan-XL Families Field Programmable Gate Arrays
    XCS05-4BG280I Spartan and Spartan-XL Families Field Programmable Gate Arrays
    XCS05-4BG84I Spartan and Spartan-XL Families Field Programmable Gate Arrays
    XCS05-4CS100C Spartan and Spartan-XL Families Field Programmable Gate Arrays
    XCS05-4CS100I Spartan and Spartan-XL Families Field Programmable Gate Arrays
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    XCS05-4BG280C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
    XCS05-4BG280I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
    XCS05-4BG84C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
    XCS05-4BG84I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
    XCS05-4CS100C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
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