- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372882 > XCS05-4PC280I (Xilinx, Inc.) Spartan and Spartan-XL Families Field Programmable Gate Arrays PDF資料下載
參數(shù)資料
| 型號： | XCS05-4PC280I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 14/66頁 |
| 文件大?。?/td> | 809K |
| 代理商： | XCS05-4PC280I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
4-14
DS060 (v1.5) March 2, 2000
The dual-port RAM signals and the CLB signals from which
they are originally derived are shown in
Table 10
.
The RAM16X1D primitive used to instantiate the dual-port
RAM consists of an upper and a lower 16 x 1 memory array.
The address port labeled A[3:0] supplies both the read and
write addresses for the lower memory array, which behaves
the same as the 16 x 1 single-port RAM array described
previously. Single Port Out (SPO) serves as the data output
for the lower memory. Therefore, SPO reflects the data at
address A[3:0].
The other address port, labeled DPRA[3:0] for Dual Port
Read Address, supplies the read address for the upper
memory. The write address for this memory, however,
comes from the address A[3:0]. Dual Port Out (DPO)
serves as the data output for the upper memory. Therefore,
DPO reflects the data at address DPRA[3:0].
By using A[3:0] for the write address and DPRA[3:0] for the
read address, and reading only the DPO output, a FIFO
that can read and write simultaneously is easily generated.
The simultaneous read/write capability possible with the
dual-port RAM can provide twice the effective data through-
put of a single-port RAM alternating read and write opera-
tions.
The timing relationships for the dual-port RAM mode are
shown in
Figure 13
.
Note that write operations to RAM are synchronous
(edge-triggered); however, data access is asynchronous.
Figure 14: Logic Diagram for the Dual-Port RAM
G
G
G
G
16 x 1
RAM
W
S
4
A[3:0]
I
R
S
4
DPRA[3:0]
G
G
G
G
16 x 1
RAM
W
S
R
S
4
4
D
WE
WCLK
G
SPO
WRITE
CONTROL
READ
OUT
DPO
WRITE
CONTROL
READ
OUT
G
G
G
Table 10: Dual-Port RAM Signals
RAM Signal
Function
CLB
Signal
DIN
F
1
-F
4
D
A[3:0]
Data In
Read Address for Single-Port.
Write Address for Single-Port
and Dual-Port.
Read Address for Dual-Port
Write Enable
Clock
Single Port Out
(addressed by A[3:0])
Dual Port Out
(addressed by DPRA[3:0])
DPRA[3:0]
WE
WCLK
SPO
G
1
-G
4
SR
K
F
OUT
DPO
G
OUT
Powered by ICminer.com Electronic-Library Service CopyRight 2003
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCS05-4PC84C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-4PC84I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-4PQ144C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-4PQ144I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-4PQ208C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCS05-4PC84C | 功能描述:IC FPGA 5V C-TEMP 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCS05-4PC84I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
| XCS05-4PQ100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-4PQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-4PQ144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。