參數(shù)資料
型號(hào)： XCS05-4TQ84C
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門陣列
文件頁(yè)數(shù)： 13/66頁(yè)
文件大小： 809K
代理商： XCS05-4TQ84C
R
DS060 (v1.5) March 2, 2000
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4-13
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Writing data to the single-port RAM is essentially the same
as writing to a data register. It is an edge-triggered (syn-
chronous) operation performed by applying an address to
the A inputs and data to the D input during the active edge
of WCLK while WE is High.
The timing relationships are shown in
Figure 13
. The High
logic level on WE enables the input data register for writing.
The active edge of WCLK latches the address, input data,
and WE signals. Then, an internal write pulse is generated
that loads the data into the memory cell.
WCLK can be configured as active on either the rising edge
(default) or the falling edge. While the WCLK input to the
RAM accepts the same signal as the clock input to the
associated CLB
’
s flip-flops, the sense of this WCLK input
can be inverted with respect to the sense of the flip-flop
clock inputs. Consequently, within the same CLB, data at
the RAM
’
s SPO line can be stored in a flip-flop with either
the same or the inverse clock polarity used to write data to
the RAM.
The WE input is active High and cannot be inverted within
the CLB.
Allowing for settling time, the data on the SPO output
reflects the contents of the RAM location currently
addressed. When the address changes, following the asyn-
chronous delay T
ILO
, the data stored at the new address
location will appear on SPO. If the data at a particular RAM
address is overwritten, after the delay T
WOS
, the new data
will appear on SPO.
Dual-Port Mode
In dual-port mode, the function generators (F-LUT and
G-LUT) are used to create a 16 x 1 dual-port memory. Of
the two data ports available, one permits read and write
operations at the address specified by A[3:0] while the sec-
ond provides only for read operations at the address spec-
ified
independently
by
DPRA[3:0].
simultaneous read/write operations at different addresses
(or even at the same address) are supported.
As
a
result,
The functional organization of the 16 x 1 dual-port RAM is
shown in
Figure 14
.
G
G
G
16 x 1
32 x 1
RAM ARRAY
W
S
D
0
or D
1
n
WE
A[n-1:0]
I
WCLK
G
SPO
R
S
WRITE
CONTROL
READ
OUT
n
Figure 12: Logic Diagram for the Single-Port RAM
NOTE: 1. The (16 x 1) x 2 configuration combines two 16 x 1 single-port RAMs, each with its own independent address bus and
data input. The same WE and WCLK signals are connected to both RAMs.
2. n = 4 for the 16 x 1 and (16 x 1) x 2 configurations. n = 5 for the 32 x 1 configuration.
X6461
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD
NEW
T
DSS
T
DHS
T
ASS
T
AHS
T
WSS
T
WPS
T
WHS
T
WOS
T
ILO
T
ILO
Figure 13: Data Write and Access Timing for RAM
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