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| 型號(hào)： | XCS20XL-3TQ256C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁(yè)數(shù)： | 42/82頁(yè) |
| 文件大小： | 863K |
| 代理商： | XCS20XL-3TQ256C |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
DS060 (v1.6) September 19, 2001
Product Specification
1-800-255-7778
R
Spartan Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and internal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report.
Spartan Output Flip-Flop, Clock-to-Out
Symbol
Description
Device
Speed Grade
Units
-4
-3
Max
Global Primary Clock to TTL Output using OFF
TICKOF
Fast
XCS05
5.3
8.7
ns
XCS10
5.7
9.1
ns
XCS20
6.1
9.3
ns
XCS30
6.5
9.4
ns
XCS40
6.8
10.2
ns
TICKO
Slew-rate limited
XCS05
9.0
11.5
ns
XCS10
9.4
12.0
ns
XCS20
9.8
12.2
ns
XCS30
10.2
12.8
ns
XCS40
10.5
12.8
ns
Global Secondary Clock to TTL Output using OFF
TICKSOF
Fast
XCS05
5.8
9.2
ns
XCS10
6.2
9.6
ns
XCS20
6.6
9.8
ns
XCS30
7.0
9.9
ns
XCS40
7.3
10.7
ns
TICKSO
Slew-rate limited
XCS05
9.5
12.0
ns
XCS10
9.9
12.5
ns
XCS20
10.3
12.7
ns
XCS30
10.7
13.2
ns
XCS40
11.0
14.3
ns
Delay Adder for CMOS Outputs Option
TCMOSOF Fast
All devices
0.8
1.0
ns
TCMOSO
Slew-rate limited
All devices
1.5
2.0
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 33.
3.
OFF = Output Flip-Flop
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCS20XL-3TQ256I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20XL-3TQ280C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20XL-3TQ280I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20XL-3TQ84C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20XL-3TQ84I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCS20XL-3TQ256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20XL-3TQ280C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20XL-3TQ280I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20XL-3TQ84C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20XL-3TQ84I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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