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| 型號： | XCS20XL-4TQG144I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 3/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SPARTAN-XL FPGA 20K 144-TQFP |
| 產(chǎn)品變化通告： | Product Discontinuation 26/Oct/2011 |
| 標準包裝： | 60 |
| 系列： | Spartan®-XL |
| LAB/CLB數(shù)： | 400 |
| 邏輯元件/單元數(shù)： | 950 |
| RAM 位總計： | 12800 |
| 輸入/輸出數(shù)： | 113 |
| 門數(shù)： | 20000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 144-LQFP |
| 供應商設備封裝： | 144-TQFP（20x20） |
| 其它名稱： | 122-1294 |
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Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
CLB Interface
A block diagram of the CLB interface signals is shown in
Figure 9. The input signals to the CLB are distributed evenly
on all four sides providing maximum routing flexibility. In
general, the entire architecture is symmetrical and regular.
It is well suited to established placement and routing algo-
rithms. Inputs, outputs, and function generators can freely
swap positions within a CLB to avoid routing congestion
during the placement and routing operation. The exceptions
are the clock (K) input and CIN/COUT signals. The K input
is routed to dedicated global vertical lines as well as four
single-length lines and is on the left side of the CLB. The
CIN/COUT signals are routed through dedicated intercon-
nects which do not interfere with the general routing struc-
ture. The output signals from the CLB are available to drive
both vertical and horizontal channels.
Programmable Switch Matrices
The horizontal and vertical single- and double-length lines
intersect at a box called a programmable switch matrix
(PSM). Each PSM consists of programmable pass transis-
tors used to establish connections between the lines (see
For example, a single-length signal entering on the right
side of the switch matrix can be routed to a single-length
line on the top, left, or bottom sides, or any combination
thereof, if multiple branches are required. Similarly, a dou-
ble-length signal can be routed to a double-length line on
any or all of the other three edges of the programmable
switch matrix.
Single-Length Lines
Single-length lines provide the greatest interconnect flexibil-
ity and offer fast routing between adjacent blocks. There are
eight vertical and eight horizontal single-length lines associ-
ated with each CLB. These lines connect the switching
matrices that are located in every row and column of CLBs.
Single-length lines are connected by way of the program-
mable switch matrices, as shown in Figure 10. Routing con-
nectivity is shown in Figure 8.
Single-length lines incur a delay whenever they go through
a PSM. Therefore, they are not suitable for routing signals
for long distances. They are normally used to conduct sig-
nals within a localized area and to provide the branching for
nets with fanout greater than one.
Figure 8: Spartan/XL CLB Routing Channels and Interface Block Diagram
PSM
CLB
PSM
8 Singles
2 Doubles
3 Longs
2 Doubles
3 Longs
2 Doubles
8 Singles
DS060_09_041901
Figure 9: CLB Interconnect Signals
CIN
Y
G3
C3
F3
COUT
G1
C1
K
F1
X
XQ
F4
C4
G4
YQ
F2
C2
G2
CLB
DS060_08_081100
Rev 1.1
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| XCS20XL-4VQ100C | 功能描述:IC FPGA 3.3V C-TEMP HP 100VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-XL 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應商設備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCS20XL-4VQ100C0090 | 制造商:Xilinx 功能描述: |
| XCS20XL-4VQ100C0167 | 制造商:Xilinx 功能描述: |
| XCS20XL-4VQ100I | 功能描述:IC FPGA 3.3V ITEMP HP 100VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-XL 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應商設備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCS20XL-4VQ144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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