參數(shù)資料
型號： XCS20XL-4VQ100C
廠商： Xilinx Inc
文件頁數(shù)： 33/83頁
文件大?。?/td> 0K
描述： IC FPGA 3.3V C-TEMP HP 100VQFP
產(chǎn)品變化通告： Product Discontinuation 26/Oct/2011
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-XL
LAB/CLB數(shù)： 400
邏輯元件/單元數(shù)： 950
RAM 位總計： 12800
輸入/輸出數(shù)： 77
門數(shù)： 20000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-VQFP（14x14）
Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
39
Product Specification
R
Product Obsolete/Under Obsolescence
Readback Abort
When the Readback Abort option is selected, a High-to-Low
transition on RDBK.TRIG terminates the Readback opera-
tion and prepares the logic to accept another trigger.
After an aborted Readback, additional clocks (up to one
Readback clock per configuration frame) may be required to
re-initialize the control logic. The status of Readback is indi-
cated by the output control net RDBK.RIP. RDBK.RIP is
High whenever a readback is in progress.
Clock Select
CCLK is the default clock. However, the user can insert
another clock on RDBK.CLK. Readback control and data
are clocked on rising edges of RDBK.CLK. If Readback
must be inhibited for security reasons, the Readback control
nets are simply not connected. RDBK.CLK is located in the
lower right chip corner.
Violating the Maximum High and Low Time
Specification for the Readback Clock
The Readback clock has a maximum High and Low time
specification. In some cases, this specification cannot be
met. For example, if a processor is controlling Readback, an
interrupt may force it to stop in the middle of a readback.
This necessitates stopping the clock, and thus violating the
specification.
The specification is mandatory only on clocking data at the
end of a frame prior to the next start bit. The transfer mech-
anism will load the data to a shift register during the last six
clock cycles of the frame, prior to the start bit of the following
frame. This loading process is dynamic, and is the source of
the maximum High and Low time requirements.
Therefore, the specification only applies to the six clock
cycles prior to and including any start bit, including the
clocks before the first start bit in the Readback data stream.
At other times, the frame data is already in the register and
the register is not dynamic. Thus, it can be shifted out just
like a regular shift register.
The user must precisely calculate the location of the Read-
back data relative to the frame. The system must keep track
of the position within a data frame, and disable interrupts
before frame boundaries. Frame lengths and data formats
are listed in Table 16 and Table 17.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCS20XL-4VQ100C0090 制造商:Xilinx 功能描述:
XCS20XL-4VQ100C0167 制造商:Xilinx 功能描述:
XCS20XL-4VQ100I 功能描述:IC FPGA 3.3V ITEMP HP 100VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-XL 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789
XCS20XL-4VQ144C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS20XL-4VQ144I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
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