參數(shù)資料
型號(hào)： XCS20XL-5PQ208C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 42/83頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 3.3V C-TEMP HP 208PQFP
產(chǎn)品變化通告： Product Discontinuation 26/Oct/2011
標(biāo)準(zhǔn)包裝： 24
系列： Spartan®-XL
LAB/CLB數(shù)： 400
邏輯元件/單元數(shù)： 950
RAM 位總計(jì)： 12800
輸入/輸出數(shù)： 160
門數(shù)： 20000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
47
Product Specification
R
Product Obsolete/Under Obsolescence
Spartan Family Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Pin-to-pin timing
parameters are derived from measuring external and inter-
nal test patterns and are guaranteed over worst-case oper-
ating conditions (supply voltage and junction temperature).
Listed below are representative values for typical pin loca-
tions and normal clock loading. For more specific, more pre-
cise, and worst-case guaranteed data, reflecting the actual
routing structure, use the values provided by the static tim-
ing analyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report.
Spartan Family Output Flip-Flop, Clock-to-Out
Symbol
Description
Device
Speed Grade
Units
-4
-3
Max
Global Primary Clock to TTL Output using OFF
TICKOF
Fast
XCS05
5.3
8.7
ns
XCS10
5.7
9.1
ns
XCS20
6.1
9.3
ns
XCS30
6.5
9.4
ns
XCS40
6.8
10.2
ns
TICKO
Slew-rate limited
XCS05
9.0
11.5
ns
XCS10
9.4
12.0
ns
XCS20
9.8
12.2
ns
XCS30
10.2
12.8
ns
XCS40
10.5
12.8
ns
Global Secondary Clock to TTL Output using OFF
TICKSOF
Fast
XCS05
5.8
9.2
ns
XCS10
6.2
9.6
ns
XCS20
6.6
9.8
ns
XCS30
7.0
9.9
ns
XCS40
7.3
10.7
ns
TICKSO
Slew-rate limited
XCS05
9.5
12.0
ns
XCS10
9.9
12.5
ns
XCS20
10.3
12.7
ns
XCS30
10.7
13.2
ns
XCS40
11.0
14.3
ns
Delay Adder for CMOS Outputs Option
TCMOSOF Fast
All devices
0.8
1.0
ns
TCMOSO
Slew-rate limited
All devices
1.5
2.0
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 34.
3.
OFF = Output Flip-Flop
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