- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4058 > XCS30-3PQ208C (Xilinx Inc)IC FPGA 5V C-TEMP 208-PQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | XCS30-3PQ208C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 5/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 5V C-TEMP 208-PQFP |
| 產(chǎn)品變化通告： | Spartan,Virtex FPGA/SCD Discontinuation 18/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | Spartan® |
| LAB/CLB數(shù)： | 576 |
| 邏輯元件/單元數(shù)： | 1368 |
| RAM 位總計(jì)： | 18432 |
| 輸入/輸出數(shù)： | 169 |
| 門數(shù)： | 30000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁
Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
13
Product Specification
R
Product Obsolete/Under Obsolescence
The four Primary Global buffers offer the shortest delay and
negligible skew. Four Secondary Global buffers have
slightly longer delay and slightly more skew due to poten-
tially heavier loading, but offer greater flexibility when used
to drive non-clock CLB inputs. The eight Global Low-Skew
buffers in the Spartan-XL devices combine short delay, neg-
ligible skew, and flexibility.
The Primary Global buffers must be driven by the semi-ded-
icated pads (PGCK1-4). The Secondary Global buffers can
be sourced by either semi-dedicated pads (SGCK1-4) or
internal nets. Each corner of the device has one Primary
buffer and one Secondary buffer. The Spartan-XL family
has eight global low-skew buffers, two in each corner. All
can be sourced by either semi-dedicated pads (GCK1-8) or
internal nets.
Using the library symbol called BUFG results in the software
choosing the appropriate clock buffer, based on the timing
requirements of the design. A global buffer should be spec-
ified for all timing-sensitive global signal distribution. To use
a global buffer, place a BUFGP (primary buffer), BUFGS
(secondary buffer), BUFGLS (Spartan-XL family global
low-skew buffer), or BUFG (any buffer type) element in a
schematic or in HDL code.
Advanced Features Description
Distributed RAM
Optional modes for each CLB allow the function generators
(F-LUT and G-LUT) to be used as Random Access Memory
(RAM).
Read and write operations are significantly faster for this
on-chip RAM than for off-chip implementations. This speed
advantage is due to the relatively short signal propagation
delays within the FPGA.
Memory Configuration Overview
There are two available memory configuration modes: sin-
gle-port RAM and dual-port RAM. For both these modes,
write operations are synchronous (edge-triggered), while
read operations are asynchronous. In the single-port mode,
a single CLB can be configured as either a 16 x 1, (16 x 1)
x 2, or 32 x 1 RAM array. In the dual-port mode, a single
CLB can be configured only as one 16 x 1 RAM array. The
different CLB memory configurations are summarized in
Table 8. Any of these possibilities can be individually pro-
grammed into a Spartan/XL FPGA CLB.
Figure 11: 5V Spartan Family Global Net Distribution
X4
ds060_11_080400
X4
4
One BUFGP
per Global Line
One BUFGP
per Global Line
Any BUFGS
BUFGP
PGCK4
SGCK4
PGCK3
SGCK3
BUFGS
BUFGP
BUFGS
IOB
BUFGS
BUFGP
SGCK1
PGCK1
SGCK2
PGCK2
IOB
X4
locals
4
CLB
locals
CLB
locals
Table 8: CLB Memory Configurations
Mode
16 x 1
(16 x 1) x 2
32 x 1
Single-Port
√√
√
Dual-Port
√
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 65801-166LF | CLINCHER RECEPTACLE ASSY GOLD |
| XCS30-3BG256C | IC FPGA 5V C-TEMP 256-PBGA |
| MPC860PVR80D4R2 | IC MPU POWERQUICC 80MHZ 357PBGA |
| IDT71T75602S133BG8 | IC SRAM 18MBIT 133MHZ 119BGA |
| IDT71T75602S100BGG8 | IC SRAM 18MBIT 100MHZ 119BGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCS30-3PQ208I | 功能描述:IC FPGA 5V I-TEMP 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCS30-3PQ208I0167 | 制造商:Xilinx 功能描述: |
| XCS30-3PQ240C | 功能描述:IC FPGA 5V C-TEMP 240-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCS30-3PQ240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-3PQ256C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。