參數資料
| 型號： | XCS30XL-5VQ100C |
| 廠商： | Xilinx Inc |
| 文件頁數： | 26/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 3.3V C-TEMP HP 100VQFP |
| 產品變化通告： | Product Discontinuation 26/Oct/2011 |
| 標準包裝： | 90 |
| 系列： | Spartan®-XL |
| LAB/CLB數： | 576 |
| 邏輯元件/單元數： | 1368 |
| RAM 位總計： | 18432 |
| 輸入/輸出數： | 77 |
| 門數： | 30000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 供應商設備封裝： | 100-VQFP（14x14） |
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Spartan and Spartan-XL FPGA Families Data Sheet
32
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
Legend:
A selection of CRC or non-CRC error checking is allowed by
the bitstream generation software. The Spartan-XL family
Express mode only supports non-CRC error checking. The
non-CRC
error
checking
tests
for
a
designated
end-of-frame field for each frame. For CRC error checking,
the software calculates a running CRC and inserts a unique
four-bit partial check at the end of each frame. The 11-bit
CRC check of the last frame of an FPGA includes the last
seven data bits.
Detection of an error results in the suspension of data load-
ing before DONE goes High, and the pulling down of the
INIT pin. In Master serial mode, CCLK continues to operate
externally. The user must detect INIT and initialize a new
configuration by pulsing the PROGRAM pin Low or cycling
VCC.
Cyclic Redundancy Check (CRC) for Configura-
tion and Readback
The Cyclic Redundancy Check is a method of error detec-
tion in data transmission applications. Generally, the trans-
mitting system performs a calculation on the serial
bitstream. The result of this calculation is tagged onto the
data stream as additional check bits. The receiving system
performs an identical calculation on the bitstream and com-
pares the result with the received checksum.
Each data frame of the configuration bitstream has four
error bits at the end, as shown in Table 16. If a frame data
error is detected during the loading of the FPGA, the config-
uration process with a potentially corrupted bitstream is ter-
minated. The FPGA pulls the INIT pin Low and goes into a
Wait state.
Table 16: Spartan/XL Data Stream Formats
Data Type
Serial Modes
(D0...)
Express Mode
(D0-D7)
(Spartan-XL only)
Fill Byte
11111111b
FFFFh
Preamble Code
0010b
11110010b
Length Count
COUNT[23:0]
COUNT[23:0](1)
Fill Bits
1111b
-
Field Check
Code
-
11010010b
Start Field
0b
11111110b(2)
Data Frame
DATA[n–1:0]
CRC or Constant
Field Check
xxxx (CRC)
or 0110b
11010010b
Extend Write
Cycle
-
FFD2FFFFFFh
Postamble
01111111b
-
Start-Up Bytes(3)
FFh
FFFFFFFFFFFFFFh
Unshaded
Once per bitstream
Light
Once per data frame
Dark
Once per device
Notes:
1.
Not used by configuration logic.
2.
11111111b for XCS40XL only.
3.
Development system may add more start-up bytes.
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