參數(shù)資料
型號(hào)： XCS40-3TQ84I
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場可編程門陣列
文件頁數(shù)： 52/82頁
文件大小： 863K
代理商： XCS40-3TQ84I
Spartan and Spartan-XL Families Field Programmable Gate Arrays
56
DS060 (v1.6) September 19, 2001
1-800-255-7778
Product Specification
R
Spartan-XL CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all Spartan-XL devices and are expressed in nano-
seconds unless otherwise noted.
Symbol
Single Port RAM
Size(1)
Speed Grade
Units
-5
-4
Min
Max
Min
Max
Write Operation
TWCS
Address write cycle time (clock K period)
16x2
7.7
-
8.4
-
ns
TWCTS
32x1
7.7
-
8.4
-
ns
TWPS
Clock K pulse width (active edge)
16x2
3.1
-
3.6
-
ns
TWPTS
32x1
3.1
-
3.6
-
ns
TASS
Address setup time before clock K
16x2
1.3
-
1.5
-
ns
TASTS
32x1
1.5
-
1.7
-
ns
TDSS
DIN setup time before clock K
16x2
1.5
-
1.7
-
ns
TDSTS
32x1
1.8
-
2.1
-
ns
TWSS
WE setup time before clock K
16x2
1.4
-
1.6
-
ns
TWSTS
32x1
1.3
-
1.5
-
ns
All hold times after clock K
16x2
0.0
-
0.0
-
ns
TWOS
Data valid after clock K
32x1
-
4.5
-
5.3
ns
TWOTS
16x2
-
5.4
-
6.3
ns
Read Operation
TRC
Address read cycle time
16x2
2.6
-
3.1
-
ns
TRCT
32x1
3.8
-
5.5
-
ns
TILO
Data Valid after address change (no Write
Enable)
16x2
-
1.0
-
1.1
ns
TIHO
32x1
-
1.7
-
2.0
ns
TICK
Address setup time before clock K
16x2
0.6
-
0.7
-
ns
TIHCK
32x1
1.3
-
1.6
-
ns
Notes:
1.
Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing.
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