參數(shù)資料
型號(hào)： XCV100E-7FG256I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 165/233頁(yè)
文件大小： 0K
描述： IC FPGA 1.8V I-TEMP 256-FBGA
產(chǎn)品變化通告： FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝： 90
系列： Virtex®-E
LAB/CLB數(shù)： 600
邏輯元件/單元數(shù)： 2700
RAM 位總計(jì)： 81920
輸入/輸出數(shù)： 176
門數(shù)： 128236
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-FBGA（17x17）
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Virtex-E 1.8 V Field Programmable Gate Arrays
R
DS022-2 (v3.0) March 21, 2014
Module 2 of 4
Production Product Specification
31
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Verilog Initialization Example
module MYMEM (CLK, WE, ADDR, DIN, DOUT);
input CLK, WE;
input [8:0] ADDR;
input [7:0] DIN;
output [7:0] DOUT;
wire logic0, logic1;
//synopsys dc_script_begin
//set_attribute ram0 INIT_00
"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string
//set_attribute ram0 INIT_01
"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string
//synopsys dc_script_end
assign logic0 = 1’b0;
assign logic1 = 1’b1;
RAMB4_S8 ram0 (.WE(WE), .EN(logic1), .RST(logic0), .CLK(CLK), .ADDR(ADDR), .DI(DIN),
.DO(DOUT));
//synopsys translate_off
defparam ram0.INIT_00 =
256h’0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF;
defparam ram0.INIT_01 =
256h’FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210;
//synopsys translate_on
endmodule
Using SelectI/O
The Virtex-E FPGA series includes a highly configurable,
high-performance I/O resource, called SelectI/O to pro-
vide support for a wide variety of I/O standards. The
SelectI/O resource is a robust set of features including pro-
grammable control of output drive strength, slew rate, and
input delay and hold time. Taking advantage of the flexibility
and SelectI/O features and the design considerations
described in this document can improve and simplify sys-
tem level design.
Introduction
As FPGAs continue to grow in size and capacity, the larger
and more complex systems designed for them demand an
increased variety of I/O standards. Furthermore, as system
clock speeds continue to increase, the need for high perfor-
mance I/O becomes more important.
While chip-to-chip delays have an increasingly substantial
impact on overall system speed, the task of achieving the
desired system performance becomes more difficult with
the proliferation of low-voltage I/O standards. SelectI/O, the
revolutionary input/output resources of Virtex-E devices,
resolve this potential problem by providing a highly configu-
rable, high-performance alternative to the I/O resources of
more conventional programmable devices. Virtex-E SelectI/O
features combine the flexibility and time-to-market advan-
tages of programmable logic with the high performance pre-
viously available only with ASICs and custom ICs.
Each SelectI/O block can support up to 20 I/O standards.
Supporting such a variety of I/O standards allows the sup-
port of a wide variety of applications, from general purpose
standard applications to high-speed low-voltage memory
buses.
SelectI/O blocks also provide selectable output drive
strengths and programmable slew rates for the LVTTL out-
put buffers, as well as an optional, programmable weak
pull-up, weak pull-down, or weak “keeper” circuit ideal for
use in external bussing applications.
Each Input/Output Block (IOB) includes three registers, one
each for the input, output, and 3-state signals within the
IOB. These registers are optionally configurable as either a
D-type flip-flop or as a level sensitive latch.
The input buffer has an optional delay element used to guar-
antee a zero hold time requirement for input signals regis-
tered within the IOB.
The Virtex-E SelectI/O features also provide dedicated
resources for input reference voltage (VREF) and output
source voltage (VCCO), along with a convenient banking
system that simplifies board design.
By taking advantage of the built-in features and wide variety
of I/O standards supported by the SelectI/O features, sys-
tem-level design and board design can be greatly simplified
and improved.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCV100E-7HQ240C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays
XCV100E-7HQ240I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays
XCV100E-7PQ240C 功能描述:IC FPGA 1.8V C-TEMP 240-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XCV100E-7PQ240I 功能描述:IC FPGA 1.8V I-TEMP 240-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XCV100E-8BG240C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays
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