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參數(shù)資料
| 型號(hào)： | XCV200-6FGG256I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1176 CLBS, 236666 GATES, 333 MHz, PBGA256 |
| 封裝： | FBGA-256 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 167K |
| 代理商： | XCV200-6FGG256I |
Virtex 2.5 V Field Programmable Gate Arrays
R
Module 3 of 4
DS003-3 (v3.2) September 10, 2002
14
1-800-255-7778
Production Product Specification
CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.
Description
Symbol
Speed Grade
Units
Min
-6
-5
-4
Combinatorial Delays
F operand inputs to X via XOR
TOPX
0.37
0.8
0.9
1.0
ns, max
F operand input to XB output
TOPXB
0.54
1.1
1.3
1.4
ns, max
F operand input to Y via XOR
TOPY
0.8
1.5
1.7
2.0
ns, max
F operand input to YB output
TOPYB
0.8
1.5
1.7
2.0
ns, max
F operand input to COUT output
TOPCYF
0.6
1.2
1.3
1.5
ns, max
G operand inputs to Y via XOR
TOPGY
0.46
1.0
1.1
1.2
ns, max
G operand input to YB output
TOPGYB
0.8
1.6
1.8
2.1
ns, max
G operand input to COUT output
TOPCYG
0.7
1.3
1.4
1.6
ns, max
BX initialization input to COUT
TBXCY
0.41
0.9
1.0
1.1
ns, max
CIN input to X output via XOR
TCINX
0.21
0.41
0.46
0.53
ns, max
CIN input to XB
TCINXB
0.02
0.04
0.05
0.06
ns, max
CIN input to Y via XOR
TCINY
0.23
0.46
0.52
0.6
ns, max
CIN input to YB
TCINYB
0.23
0.45
0.51
0.6
ns, max
CIN input to COUT output
TBYP
0.05
0.09
0.10
0.11
ns, max
Multiplier Operation
F1/2 operand inputs to XB output via AND
TFANDXB
0.18
0.36
0.40
0.46
ns, max
F1/2 operand inputs to YB output via AND
TFANDYB
0.40
0.8
0.9
1.1
ns, max
F1/2 operand inputs to COUT output via AND
TFANDCY
0.22
0.43
0.48
0.6
ns, max
G1/2 operand inputs to YB output via AND
TGANDYB
0.25
0.50
0.6
0.7
ns, max
G1/2 operand inputs to COUT output via AND
TGANDCY
0.07
0.13
0.15
0.17
ns, max
Setup and Hold Times before/after Clock CLK(1)
Setup Time / Hold Time
CIN input to FFX
TCCKX/TCKCX
0.50 / 0
1.0 / 0
1.2 / 0
1.3 / 0
ns, min
CIN input to FFY
TCCKY/TCKCY
0.53 / 0
1.1 / 0
1.2 / 0
1.4 / 0
ns, min
Notes:
1.
A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCV200-6FGG456I | FPGA, 1176 CLBS, 236666 GATES, 333 MHz, PBGA456 |
| XCV200-6PQG240I | FPGA, 1176 CLBS, 236666 GATES, 333 MHz, PQFP240 |
| XCV200-6BGG256I | FPGA, 1176 CLBS, 236666 GATES, 333 MHz, PBGA256 |
| XCV200-6BGG352I | FPGA, 1176 CLBS, 236666 GATES, 333 MHz, PBGA352 |
| XD010-04S-D4FY | 350 MHz - 600 MHz RF/MICROWAVE WIDE BAND HIGH POWER AMPLIFIER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV200-6PQ240C | 功能描述:IC FPGA 2.5V C-TEMP 240-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCV200-6PQ240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XCV200-6PQG240C | 制造商:Xilinx 功能描述:FPGA VIRTEX 236.666K GATES 5292 CELLS 333MHZ 0.22UM 2.5V 240 - Trays |
| XCV200E | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XCV200E-6BG240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
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