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| 型號(hào)： | XCV400E-7PQ240C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 68/233頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 240-PQFP |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-E |
| LAB/CLB數(shù)： | 2400 |
| 邏輯元件/單元數(shù)： | 10800 |
| RAM 位總計(jì)： | 163840 |
| 輸入/輸出數(shù)： | 158 |
| 門數(shù)： | 569952 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 240-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 240-PQFP（32x32） |
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Virtex-E 1.8 V Field Programmable Gate Arrays
R
Module 2 of 4
DS022-2 (v3.0) March 21, 2014
10
Production Product Specification
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Data Registers
The primary data register is the Boundary Scan register.
For each IOB pin in the FPGA, bonded or not, it includes
three bits for In, Out, and 3-State Control. Non-IOB pins
have appropriate partial bit population if input-only or out-
put-only. Each EXTEST CAPTURED-OR state captures all
In, Out, and 3-state pins.
The other standard data register is the single flip-flop
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream Boundary Scan
device.
The FPGA supports up to two additional internal scan
chains that can be specified using the BSCAN macro. The
macro provides two user pins (SEL1 and SEL2) which are
decodes of the USER1 and USER2 instructions respec-
tively. For these instructions, two corresponding pins (T
DO1 and TDO2) allow user scan data to be shifted out of
TDO.
Likewise, there are individual clock pins (DRCK1 and
DRCK2) for each user register. There is a common input pin
(TDI) and shared output pins that represent the state of the
TAP controller (RESET, SHIFT, and UPDATE).
Bit Sequence
The order within each IOB is: In, Out, 3-State. The
input-only pins contribute only the In bit to the Boundary
Scan I/O data register, while the output-only pins contrib-
utes all three bits.
From a cavity-up view of the chip (as shown in EPIC), start-
ing in the upper right chip corner, the Boundary Scan
data-register bits are ordered as shown in Figure 12.
BSDL (Boundary Scan Description Language) files for Vir-
tex-E Series devices are available on the Xilinx web site in
the File Download area.
Identification Registers
The IDCODE register is supported. By using the IDCODE,
the device connected to the JTAG port can be determined.
The IDCODE register has the following binary format:
vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1
where
v = the die version number
f = the family code (05 for Virtex-E family)
a = the number of CLB rows (ranges from 16 for
XCV50E to 104 for XCV3200E)
c = the company code (49h for Xilinx)
The USERCODE register is supported. By using the USER-
CODE, a user-programmable identification code can be
loaded and shifted out for examination. The identification
code (see Table 7) is embedded in the bitstream during bit-
stream generation and is valid only after configuration.
Note:
Attempting to load an incorrect bitstream causes
configuration to fail and can damage the device.
Including Boundary Scan in a Design
Since the Boundary Scan pins are dedicated, no special
element needs to be added to the design unless an internal
data register (USER1 or USER2) is desired.
If an internal data register is used, insert the Boundary Scan
symbol and connect the necessary pins as appropriate.
Figure 12: Boundary Scan Bit Sequence
Bit 0 ( TDO end)
Bit 1
Bit 2
Right half of top-edge IOBs (Right to Left)
GCLK2
GCLK3
Left half of top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
M1
M0
M2
Left half of bottom-edge IOBs (Left to Right)
GCLK1
GCLK0
Right half of bottom-edge IOBs (Left to Right)
DONE
PROG
Right-edge IOBs (Bottom to Top)
CCLK
(TDI end)
990602001
Table 7: IDCODEs Assigned to Virtex-E FPGAs
FPGA
IDCODE
XCV50E
v0A10093h
XCV100E
v0A14093h
XCV200E
v0A1C093h
XCV300E
v0A20093h
XCV400E
v0A28093h
XCV600E
v0A30093h
XCV1000E
v0A40093h
XCV1600E
v0A48093h
XCV2000E
v0A50093h
XCV2600E
v0A5C093h
XCV3200E
v0A68093h
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASC43DRAS | CONN EDGECARD 86POS .100 R/A DIP |
| AMC30DRAN | CONN EDGECARD 60POS .100 R/A DIP |
| XCV400E-6PQ240I | IC FPGA 1.8V I-TEMP 240-PQFP |
| 24LC1026-E/SN | IC EEPROM 1024KB 400KHZ 8SOIC |
| 747580-6 | CONN FERRULE STRAIGHT DB37/50 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV400E-7PQ240I | 功能描述:IC FPGA 1.8V I-TEMP 240-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XCV400E-7PQG240C | 制造商:Xilinx 功能描述:FPGA VIRTEX-E 129.6K GATES 10800 CELLS 400MHZ 0.18UM 1.8V 24 - Trays |
| XCV400E-8BG240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV400E-8BG240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
| XCV400E-8BG432C | 功能描述:IC FPGA 1.8V C-TEMP 432-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
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