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參數(shù)資料
| 型號(hào)： | XPC755BRX400LD |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大?。?/td> | 40K |
| 代理商： | XPC755BRX400LD |
MPC7450/MPC7451
HIGH PERFORMANCE
HOST MICROPROCESSOR
Fact Sheet
60x/MPX bus interface
Completion
Unit
Instruction Fetch
Branch Unit
Dispatch Unit
32 KB
Instruction
Cache
Sequencer Unit
BHT/
BTIC
AltiVec Issue
GPR Issue
FPR Issue
CFX SFXO SFX1 SFX2
GPRs
Rename
Buffers
LSU
FPRs
Rename
Buffers
FPU
F
C
S
P
VRs
Rename
Buffers
32 kB
Data
Cache
AltiVec Engine
Interface
to Memory
Sub-System
Unified L2 Cache/Tag L3 Control
System Interface Unit
L
MPC7450/MPC7451 BLOCK DIAGRAM
SUPERSCALAR MICROPROCESSOR
MPC7450/MPC7451 mcroprocessors feature a high-frequency superscalar G4 core,
capable of issuing four instructions per clock cycle (three instructions + branch) into 11
independent execution units:
Four integer units (3 simple + 1 complex)
Double-precision floating-point unit
Four AltiVec units (simple, complex, floating, and permute)
Load/store unit
Branch processing unit
CACHE AND MMU SUPPORT
The MPC7450/MPC7451 mcroprocessor has separate 32 KB, physically addressed
instruction and data caches. Both L1 caches feature cache way locking and are eight-way
set associative. For greater speed, the L2 cache has been integrated on-chip with a 256-
bit interface to L1 which operates at processor frequency. This L2 is 256 kB eight-way set
The MPC7450/MPC7451 host processor is a high-
performance, low-power 32-bit implementation of the
PowerPC RISC architecture with a full 128-bit
implementation of Motorola’s AltiVec technology. This
mcroprocessor is ideal for leading-edge computing, em
bedded network control, and signal processing
applications. The MPC7450/MPC7451 has a deep, seven-
stage pipeline with 11 execution units. The L2 cache has
been integrated onto the die for greater speed, and
supports a large backside L3 cache with a 64-bit
datapath. The MPC7450/MPC7451 offers increased
address space and high-bandwidth MPX bus with
mnimzed signal setup times and reduced idle cycles to
increase bus bandwidth to a maximumspeed of 133 MHz.
MPC7450/MPC7451 processors offer single-cycle,
throughput, double-precision, floating-point performance
and full symmetric multi-processing (SMP) capabilities.
Finally, the MPC7450/MPC7451 is software-compatible
with existing MPC6xx, MPC7xx, and MPC74xx host
processors and exploits the full potential of AltiVec
technology.
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